200+ applicants

Company

Original Job Post

Infinera · 2 days ago

ASIC Physical Design Engineer

San Jose, CA

Full-time

Onsite

Senior Level

5+ years exp

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Responsibilities

Perform physical implementation steps including floor planning, place and route, power/clock distribution for congestion analysis and timing closure at block level as well as full chip

Work with logic designers to drive feasibility studies and explore design trade-off for physical design closure

Perform technical evaluations of vendor, process nodes and IP and provide recommendations

Develop physical design methodologies and automation scripts for various implementation steps from Synthesis to GDSII

Perform static timing analysis, create timing constraints and validation, critical path analysis, timing closure and timing sign-off

Qualification

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ASIC Physical DesignRTL to GDSIIIC DesignImplementation FlowsPlace & Route ToolsTiming ToolsScripting TCLScripting PythonScripting Perl

Required

5+ years of experience in ASIC physical design flow and methodologies in 5/7nm and 16nm process nodes

Solid knowledge of full design cycle from RTL to GDSII and understanding of underlying concepts of IC design, implementation flows and methodologies for deep submicron design

Experience with EDA Place & Route tools like ICC2 or Innovus or similar tools and Timing tools like Primetime or similar

Scripting experience in TCL, python or perl

Bachelor's Degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics with very good academics

Benefits

Paid leave

Medical, dental, and vision coverage

401(k)

Life and disability insurance

Company

Infinera

Glassdoor

4.2

Infinera Corporation provides optical networking systems based on photonic integration technology in the United States.

Founded in 2000

San Jose, California, USA

1,001-5,000 employees

http://www.infinera.com

H1B Sponsorship

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2020 (43)