200+ applicants
Cadence Design Systems · 4 days ago
RTL Senior Principal Digital Design Engineer
San Jose, CA
Full-time
Hybrid
Senior Level
$150K/yr - $280K/yr
5+ years exp
Wonder how qualified you are to the job?
Maximize your interview chancesAerospaceElectronic Design Automation (EDA)
Hiring Manager
Mark Apton
Insider Connection @Cadence Design Systems
Responsibilities
Digital microarchitecture definition and documentation
RTL logic design, debug, and functional verification
IP integration and verification
Familiarity with PMA/PMD/PCS layers of the Ethernet protocol
Understanding of digital architecture trade-offs for power, performance, and area
Handling multiple asynchronous clock domains and their crossings
Lint checks and resolution of errors
Synthesis timing constraints, static timing analysis, and constraint development
Understanding of fundamental physical design flows and stages
Impacts of analog and mixed-signal design on digital-on-top development flow
Excellent communication skills, self-motivation, and organization
Experience with FPGA and/or emulation platform
Firmware development of embedded microcontroller systems
Qualification
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Required
At least 5 plus years of actual work experience
Thorough understanding of the end-to-end digital design flow
Digital microarchitecture definition and documentation
RTL logic design, debug and functional verification
IP integration and verification
Understanding of digital architecture trade-offs for power, performance, and area
Understanding of proper handling of multiple asynchronous clock domains and their crossings
Understanding of Lint checks and proper resolution of errors
Understanding synthesis timing constraints, static timing analysis and constraint development
Understanding of fundamental physical design flows and stages
Understanding impacts of analog and mixed-signal design and verification on digital-on-top development flow
Excellent communication skills
Self-motivated and well organized
Substantial experience with Verilog
Excellent logic and debug skills
Preferred
Familiar with the PMA/PMD/PCS layers of the Ethernet protocol
Experience with FPGA and/or emulation platform
Firmware development of embedded microcontroller systems
Engineering expertise in mixed-signal IP development procedures
Ethernet connectivity protocol knowledge
Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure
Compensation may vary based on factors such as qualifications, skill level, competencies and work location
Benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more
Benefits
Paid vacation and paid holidays
401(k) plan with employer match
Employee stock purchase plan
A variety of medical, dental and vision plan options
Company
Cadence Design Systems
Cadence Design Systems develops electronic design automation, software, hardware and silicon intellectual property technologies.
5,001-10,000 employees
H1B Sponsorship
Cadence Design Systems has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Trends of Total Sponsorships
2023 (239)
2022 (276)
2021 (265)
2020 (254)
Funding
Current Stage
Public CompanyTotal Funding
unknown1998-02-20IPO· nasdaq:CDNS
Leadership Team
Jim Cowie
Advisor to the CEO
Alberto Sangiovanni Vincentelli
Co-founder
Recent News
2024-04-26
2024-04-26
Company data provided by crunchbase
