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Company

Original Job Post

Cadence Design Systems · 2 days ago

Sr Design Verification Engineering Manager

Columbia, MD

Full-time

Onsite

Mid, Senior Level

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AerospaceElectronic Design Automation (EDA)

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Responsibilities

The role requires the management of a SerDes DV group focusing on MDV verification including: Constrained Random Functional Verification, Formal Property Verification, project DV status and execution, and mentorship of junior engineers.

The role requires the ability to work with the existing functional verification environment, addition of new features into the verification environment, ensuring various customer configurations are clean as part of verification regressions.

The role will require customer interactions including pre and post-sales activities: DV methodology review, customer support.

Participate in Technical alignment with verification experts in defining verification strategy, architecting verification environment.

Represent DV and technically work/lead team interactions with RTL, analog/modeling, PD teams for design verification tasks.

Contribute towards defining, developing and deploying new functional verification methodologies.

Qualification

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VerilogUVMOVMERMAssertionsFunctional CoverageCode CoverageRTLGLSPower-aware RTLFormal verificationGate-level timing-timing simulationsAnalog modellingMixed-mode simulationsAutomotive IP verificationEmulation exposure

Required

Strong background in functional verification fundamentals

Verification environment planning & development

Test plan creation

Prior digital verification experience in serial bus multiprotocol PHY IP’s (SerDes IP especially PCIe and other protocols)

Expertise in Verilog, HVL (SV, e) with UVM/OVM/eRM methodology

Experience in assertions development/closure, constraint randomization, functional coverage, code coverage

Strong RTL and GLS sim debug skills

Preferred

Power-aware RTL set-up, simulation and debug

Formal verification

Gate-level timing-timing simulations

Some experience or understanding of Analog modelling

Mixed-mode simulations with Analog/digital (AMS)

Exposure to Automotive IP verification (fault injection)

Emulation exposure

Company

Cadence Design Systems

Glassdoor

4.3

Cadence Design Systems develops electronic design automation, software, hardware and silicon intellectual property technologies.

Founded in 1988

San Jose, California, USA

5,001-10,000 employees

https://www.cadence.com

H1B Sponsorship

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2020 (254)