Cisco · 5 days ago
ASIC Verification Engineer
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Communications InfrastructureEnterprise Software
Insider Connection @Cisco
Responsibilities
Maintaining existing DV environments and enhancing them
Constructing testbench including scoreboard, agents, sequencers, and monitors for new blocks
Writing test plan, developing testcases, debugging regression failures, and driving to module verification closure
Ensuring complete verification coverage through implementation and review of code and functional coverage
Qualification
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Required
Hands-on and deep understanding of System Verilog and UVM methodology
Experience in verifying complex blocks, clusters and top level for SoC
Can build testbenches from scratch, hands on experience with System Verilog constraints, structures and classes
Ability to debug issues independently
Proficient in functional coverage and constrained random DV environments
Scripting skills: Perl and/or Python scripting
Strong domain experience in one or more protocols in a plus – PCIe, CXL, Ethernet, AHB/AXI, DDR, MMU
Experience with Veloce/HAPS is a plus
Formal verification (iev/vc formal) knowledge is a plus
Preferred
Strong domain experience in one or more protocols in a plus – PCIe, CXL, Ethernet, AHB/AXI, DDR, MMU
Experience with Veloce/HAPS is a plus
Formal verification (iev/vc formal) knowledge is a plus
Post silicon bring up and debug in lab skill is a plus
Company
Cisco
Cisco develops, manufactures, and sells networking hardware, telecommunications equipment, and other technology services and products.
H1B Sponsorship
Cisco has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Trends of Total Sponsorships
2023 (784)
2022 (1945)
2021 (2392)
2020 (1283)
Funding
Current Stage
Public CompanyTotal Funding
unknown1990-02-23IPO· nasdaq:CSCO
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