126 applicants

Company

Original Job Post

Wipro · 1 week ago

RTL Engineer

San Francisco, CA

Full-time

Onsite

Senior Level

10+ years exp

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Hiring Manager

Ram K.

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Responsibilities

10+ years of experience in RTL/Verilog writing.

Expertise in static checking like CDC, Lint, RDC, Spyglass DFT along with module integration.

Logic design, micro-architecture, and RTL coding.

Experience in Synthesis and understanding of timing concepts for ASIC.

Design experience in complex protocols such as DDR, USB, SATA, PCIe controller.

Hands-on experience in Multi Clock designs and Asynchronous interface.

Utilize tools in all phases of ASIC development such as Lint, CDC, Simulation, etc.

Qualification

Find out how your skills align with this job's requirements. If anything seems off, you can easily click on the tags to select or unselect skills to reflect your actual expertise.

RTL/Verilog WritingStatic CheckingCDCLintRDCSpyglass DFTModule IntegrationLogic DesignMicro-architectureRTL CodingVerilogSystem VerilogASIC Timing ConceptsMulti Clock DesignsAsynchronous InterfaceASIC Development ToolsSimulationDDR designUSB designSATA designPCIe design

Required

10+ years of experience in RTL/Verilog writing.

Have expertise in static checking like CDC, Lint, RDC, Spyglass DFT along with module integration

Logic design /micro-architecture /RTL coding

Expertise in Verilog & System Verilog

Experience in Synthesis /Understanding of timing concepts for ASIC is required.

Hands on experience in Multi Clock designs, Asynchronous interface is a must.

Experience on tools utilized in all phases of ASIC development such as Lint, CDC, Simulation etc. is required.

Preferred

Experience in design of DDR / USB /SATA/ PCIe controller or such complex protocols is a plus.

Company

Wipro

Glassdoor

3.7

Wipro is a technology services and consulting company focused on building solutions that address clients’ digital transformation needs.

Founded in 1945

Bengaluru, Karnataka, IND

10,001+ employees

http://www.wipro.com

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