200+ applicants

Company

Original Job Post

Groq · 1 week ago

Senior Physical Design Engineer

Mountain View, CA

Full-time

Onsite

Senior Level

$182K/yr - $365K/yr

10+ years exp

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Responsibilities

Technical Lead for full chip integration activities; drive development and deployment of methodologies for these tasks both internally and with ASIC design partner in leading technology nodes.

Own and drive the overall Global Clock design including simulations and work closely with ASIC design partner in implementing the Global Clocks.

Lead and own Sign-off activities like STA, EMIR, Physical Verification from defining the methodology to running these at block and full chip level.

Own and drive execution of blocks from Synthesis, P&R to Timing Sign-off, Physical Sign-off and Electrical Sign-off.

Collaborate closely with the Microarchitecture/RTL team to help drive PPA improvements and resolve design issues.

Influence tools, flows and overall RTL to GDS2 physical design methodology with a data-driven approach.

Qualification

Find out how your skills align with this job's requirements. If anything seems off, you can easily click on the tags to select or unselect skills to reflect your actual expertise.

Physical DesignHigh-Speed ProcessorsPlacementRoutingTiming AnalysisPower OptimizationStatic Timing AnalysisClock Domain DesignsCTS MethodologiesPower Grid DesignUPF/CPFFormal Equivalency ChecksLow Power Rule CheckEDA ToolsCadence GenusCadence InnovusCadence TempusSynopsys Fusion CompilerSynopsys ICC2Synopsys PrimetimeAnsys RedhawkJoulesPTPXAutomation SkillsTCLPythonPerlMentoring

Required

BS in Electrical Engineering or Computer Engineer or related degree required; advanced degrees (MS, PhD) a plus.

10+ years of meaningful industry experience and a background in block/top level physical design of high-speed processors (i.e. Graphics, Microprocessors, Network Processors, or Mobile / Multimedia SOCs)

Proven track record of implementing designs through synthesis, placement, CTS, Routing, Extraction, Timing and Physical/Electrical Verification

Strong hands on experience in implementing multi-voltage, multi-clock domain designs

Expert in different CTS methodologies, global and block level clock distribution

Strong experience with Static Timing Analysis from defining methodologies to running STA at block and top level.

Expert in implementing PD power optimization techniques and have a keen eye to look for power reduction options throughout the PD cycle.

Strong understanding of timing constraints, timing analysis, power grid design, power analysis (EMIR/di/dt), ECO generation and MCMM STA signoff

Deep understanding of low power format like UPF/CPF

Experience in formal equivalency checks, Low Power Rule check and verification.

Expert in industry standard EDA tools like Cadence Genus/Innovus/Tempus, Synopsys Fusion Compiler/ICC2/Primetime, Ansys Redhawk, Joules/PTPX

Strong Automation skills using scripting languages like TCL, Python, Perl etc.

Benefits

Equity

Benefits

Company

Groq

Groq radically simplifies compute to accelerate workloads in artificial intelligence, machine learning, and high-performance computing.

Founded in 2016

Mountain View, California, USA

51-200 employees

http://groq.com

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