Andes Technology Corporation · 4 days ago
RISC-V Design Verification Engineer
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Responsibilities
Communication with peers to discuss technical details
Analyze CPU architecture and microarchitecture implementations, and devising best methods to verify them
Identify and resolve engineering issues ranging from functional verification, code coverage, Formal proofs, verification reports
Hands-on verification work including verification regression management, debugging and bug-reports
Provide technical guidance to junior members of the team
Technical documentation
Qualification
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Required
Bachelor’s or Master’s degree in related engineering field
Strong communication skills
Experience using Verilog, System Verilog
Strong mastery using Unix and scripting languages such as make, shell, perl or python
Preferred
Experience of CPU architecture (multi-core coherence, FPU, DSP, interrupt, Vector, Security, Reset and CDC, Debug)
Experience with ground-up test-benches development
Experience with functional coverage-driven verification
Familiar with stimulus generation for constrained random simulation. Experience coding in assembly languages
Experience in UVM, formal, coverage grading, coverage analysis, bug tracking
Patience and good leadership skills
Strong desire to learn and willing to devote extra effort to achieve perfection
Strong team player and possess a positive attitude
Company
Andes Technology Corporation
As a Founding Premier member of RISC-V International, Andes Technology Corporation is now a leading embedded processor intellectual property supplier in the world.
Funding
Current Stage
Growth StageTotal Funding
unknown2010-10-01Series Unknown· Undisclosed
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