Ciena · 3 days ago
Senior ASIC Verification Engineer
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Responsibilities
Develop test benches and tests for FPGAs and ASICs.
Assist in root-causing RTL bugs.
Develop verification models.
Draft detailed test plans.
Partake in test plan and coverage analysis of the block and SOC-level verification.
Qualification
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Required
Bachelor / Master or PhD degree in Electrical Engineering coupled with proven experience in ASIC development with Verilog.
Experience with ASIC design verification, synthesis, timing/power analysis and DFT.
Minimum 5 years of work experience is required in ASIC Verification, including proficiency in UVM and System Verilog.
Experience with modern SoC design architectures, ARM/MiPs type processor cores, Ethernet, Networking, and Data Communications.
Strong debug and lab experience.
Preferred
Knowledge of high-performance and low-power design techniques.
Knowledge of FPGA and emulation platforms. Knowledge of SOC architecture.
Knowledge of assertion-based formal verification.
Proficient with a scripting language like Perl.
Benefits
Medical, dental, and vision plans
401(K) with company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
Paid holidays, sick leave, and vacation time
Paid Family Leave and other leaves of absence
Company
Ciena
Ciena collaborates with customers to unlock the strategic potential of their networks and and change the way they perform and compete.
H1B Sponsorship
Ciena has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Trends of Total Sponsorships
2023 (31)
2022 (38)
2021 (31)
2020 (37)
Funding
Current Stage
Public CompanyTotal Funding
unknown1997-02-07IPO· nyse:CIEN
1995-12-01Series C· Undisclosed
1994-12-01Series B· Undisclosed
Recent News
2024-05-31
2024-05-31
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