Trilyon, Inc. · 2 days ago
Senior RTL Design Engineer
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Insider Connection @Trilyon, Inc.
Responsibilities
Perform RTL design of digital components in Verilog/systemverilog.
Analyze/fix Lint and CDC errors of the components.
Guarantee quality/timely deliverables meeting the project’s schedule.
Help to improve/automate the design process.
Qualification
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Required
Bachelor's or Master's in Computer Engineering
RTL design using Verilog HDL
Read and comprehend the System on Chip level architectural specification
Write microarchitecture specifications for new and modified functions
Linting and simulation of design
Work with synthesis and backend teams for physical implementation
Perform RTL design of digital components in Verilog/systemverilog
Analyze/fix Lint and CDC errors of the components
Guarantee quality/timely deliverables meeting the project’s schedule
Help to improve/automate the design process
Preferred
Knowledge of RISK-V processor integration Express
Multi-clock domain designs
Design constraints for synthesis and static timing analysis
Knowledge of AXI/AMBA protocol
Knowledge of front-end RTL design tools and methodologies
Knowledge of scripting languages like Perl, tcl, or shell