RTL Design Engineer @ HCLTech | Jobright.ai
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HCLTech · 1 week ago

RTL Design Engineer

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Responsibilities

Contribute to micro-architecture specification for SoC design block
Participated in 2-3 SoC projects
Participate in SoC Chip Architecture specification reviews
Must have extensive experience in Micro-architecture design for SoC sub-blocks
Interact with SoC integration, verification, and physical design teams and also with IP vendors
Extensive experience in SoC RTL coding (Verilog or System-Verilog)
Experience in RTL Code Linting and CDC checks
Experience in RTL integration using Industry standard tools, is an added advantage
Handle complete responsibility of an entire block starting from Micro-architecture specifications, RTL implementation, Linting, CDC, Synthesis/STA
Experience in low power design techniques
Good understanding of DFx design techniques
Good appreciation of AXI/AHB bus protocol, GigBE, USB, NAND Flash Technology, PCIe Gen2/3 Host interface, DDR2/3 memory interfaces etc.
Experience in PCIe, HBM memory protocol is preferred

Qualification

Find out how your skills align with this job's requirements. If anything seems off, you can easily click on the tags to select or unselect skills to reflect your actual expertise.

Micro-architecture designSoC projectsRTL codingRTL Code LintingCDC checksSynthesis/STALow power designDFx designAXI/AHB bus protocolGigBEUSBNAND Flash TechnologyPCIe Gen2/3 Host interfaceDDR2/3 memory interfacesRTL IntegrationIndustry Standard ToolsPCIeHBM Memory Protocol

Required

Contribute to micro-architecture specification for SoC design block
Participated in 2-3 SoC projects
Participate in SoC Chip Architecture specification reviews
Must have extensive experience in Micro-architecture design for SoC sub-blocks
Interact with SoC integration, verification and physical design teams and also with IP vendors
Extensive experience in SoC RTL coding (Verilog or System-Verilog)
Experience in RTL Code Linting and CDC checks
Handle complete responsibility of an entire block starting from Micro-architecture specifications, RTL implementation, Linting, CDC, Synthesis/STA
Experience in low power design techniques
Good understanding of DFx design techniques
Good appreciation of AXI/AHB bus protocol, GigBE, USB, NAND Flash Technology, PCIe Gen2/3 Host interface, DDR2/3 memory interfaces etc.

Preferred

Experience in RTL integration using Industry standard tools is an added advantage
Experience in PCIe, HBM memory protocol is preferred

Company

HCLTech is a global technology company, home to more than 224,000 people across 60 countries, delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products.

H1B Sponsorship

HCLTech has a track record of offering H1B sponsorships. Please note that this does not guarantee sponsorship for this specific role. Below presents additional info for your reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Trends of Total Sponsorships
2023 (2837)
2022 (3809)
2021 (3725)
2020 (4406)

Funding

Current Stage
Public Company
Total Funding
$220M
Key Investors
Chrys Capital
2008-07-10Post Ipo Equity· $220M
2001-01-24IPO· nse:HCLTECH

Leadership Team

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C Vijayakumar
Chief Executive Officer
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Alan Flower
Senior Vice President - CTO EMEA & Global Head, Cloud Native Labs
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Company data provided by crunchbase
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