PRI Global · 1 week ago

Physical Design Engineer

United States

Contract

Remote

Senior Level

10+ years exp

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Arun K

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Responsibilities

Run Logic/Physical Synthesis and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them.

Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities.

Perform RTL Lint and work with the Designers to create waivers.

Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks.

Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power).

Qualification

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Backend ImplementationTiming ClosurePower AnalysisRTL SynthesisDesign OptimizationPower Performance AreaEDA ToolsScripting LanguagesPythonTCLFunctional TeamsCommunication