Synapse Design Inc. · 1 week ago
Senior Design Verification Engineer
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Responsibilities
Create test benches in SystemVerilog with UVM
Utilize advanced verification techniques
Write tools and scripts to enhance the verification process
Qualification
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Required
BS, MS in computer science or engineering
Experience with C/C++
Experience with SystemVerilog and UVM
Experience with advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verifiers.
Good software skills
Good problem-solving and debugging skills.
Preferred
Understanding of overall ASIC/SOC architecture is a plus.
Company
Synapse Design Inc.
Since its founding in 2003, Synapse Designs' specialized design and engineering services have made us the preferred partner to numerous top-tier semiconductor and systems companies around the world.
H1B Sponsorship
Synapse Design Inc. has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Trends of Total Sponsorships
2023 (2)
2022 (11)
2021 (15)
2020 (9)
Funding
Current Stage
Late StageTotal Funding
unknown2021-06-29Acquired· by Quest Global
2015-05-28Debt Financing· Undisclosed
2015-04-10Debt Financing· Undisclosed
Leadership Team
Recent News
linkedin.com
2022-08-26
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