Be an early applicantLess than 25 applicants

Company

Original Job Post

Google · 3 days ago

Silicon Design Lead

Mountain View, CA

Full-time

Onsite

Senior Level

$177K/yr - $266K/yr

8+ years exp

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Responsibilities

Lead a team that delivers fabric interconnect IP, sub-system.

Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc.

Oversee RTL development, debug functional/performance simulations.

Meet schedule commitments and provide strong support to customers.

Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up.

Qualification

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RTL DesignVerilogSystem VerilogMicroarchitectureARM-based SoCsASIC MethodologyPeople ManagementLeadershipIP DesignLow Power EstimationTiming ClosureTeam ManagementRoadmap DevelopmentProblem-Solving

Required

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

8 years of experience with RTL design using Verilog/System Verilog and microarchitecture.

4 years of experience in people management, leading IP/SoC design team for low power SoCs.

Experience with ARM-based SoCs, interconnects, and ASIC methodology.

Preferred

Master’s degree in Electrical/Computer Engineering, or a related field.

15 years of experience with IP design for clocking, interconnects, and peripherals.

Experience with methodologies for low power estimation, timing closure, and synthesis.

Experience managing technical teams.

Ability to drive multi-generational roadmap for IP/SoC development.

Company

Google

Glassdoor

4.4

Google is a multinational corporation that specializes in Internet-related services and products. It is a sub-organization of Alphabet.

Founded in 1998

Mountain View, California, USA

10,001+ employees

https://www.google.com

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