130 applicants

Company

Original Job Post

Groq · 1 week ago

Senior ASIC Design Verification Engineer

Mountain View, CA

Full-time

Onsite

Senior Level

$182K/yr - $318K/yr

10+ years exp

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Responsibilities

Verify hardware features of Language Process Unit (LPU).

Collaborate within the Hardware Team to design and verify features on LPU chips in simulation, emulation and silicon.

Develop and implement advanced verification environments and methodologies for complex ASIC designs.

Implement and optimize automated verification flows to improve productivity and efficiency.

Utilize formal verification techniques to rigorously verify critical design properties and ensure compliance with specifications.

Stay updated on the latest trends and advancements in ASIC design verification and incorporate innovative techniques into the verification process.

Support silicon bring-up and debug.

Be a productivity multiplier. Contribute to identifying and adopting engineering best practices within the verification team and interactions with cross-functional teams at Groq.

Innovate. Contribute to developing future verification strategies for validating future accelerator chips and hardware architectures for ML workloads.

Qualification

Find out how your skills align with this job's requirements. If anything seems off, you can easily click on the tags to select or unselect skills to reflect your actual expertise.

Design VerificationTestbench DevelopmentSystemVerilogUVMConstrained TestingPower VerificationUPFNetlist SimulationFormal VerificationPython ScriptingPerl ScriptingASIC Design FlowMachine LearningSilicon Bring-upDebuggingManufacturing ATE SupportBug-Free DeliveryCommunication

Required

BS degree in electrical engineering, or related fields, or equivalent practical experience; advance degrees (MS or PhD) is a plus

10+ years design verification experience of building testbenches environments and design verification processes

Experience with building block and SOC testbench development

Good familiarity with SystemVerilog and UVM

Good familiarity with randomly constrained testing methodologies

Good familiarity with power verification strategies and UPF

Good familiarity with netlist simulation

Good familiarity with formal verification flow and tools

Experience in Python and/or Perl scripting

Knowledge of ASIC design flow

Knowledge of applying machine learning to ASIC verification flow

Knowledge of silicon bring-up, debug, and manufacturing ATE support

Proven track record of delivering bug-free silicon

Preferred

Excellent verbal and written communication skills to clearly communicate concepts in written and verbal form to stakeholders

Company

Groq

Groq radically simplifies compute to accelerate workloads in artificial intelligence, machine learning, and high-performance computing.

Founded in 2016

Mountain View, California, USA

51-200 employees

http://groq.com

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