myGwork - LGBTQ+ Business Community · 2 days ago
Sr. Physical Design Engineer - Full Chip
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Responsibilities
Perform floorplanning, pin and feedthrough planning, repeater insertion, power grid generation and assembly of partitions.
Drive efficiency and quality improvements to the overall FC methodology including floorplan optimization for better utilization/QoR/runtime and timing and physical aware feedthrough/pin placement.
Coordinate collateral handoffs between the FC Design team and other functions within back-end design such as Clocking, Power Delivery and Partition synthesis/APR.
Drive physical design and timing closure including FEV, LVS, DRC, and reliability verification (IR drop / EM analysis).
Supervise and mentor other engineers.
Qualification
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Required
Bachelor's degree or higher in EE, CE, or CS
10+ years or more of practical semiconductor implementation experience
Scripting experience with Perl, Python, tcl, shell and drive to automate flows
Proficiency in chip front-end and back-end implementation tools such as Fusion compiler, Design Compiler, ICC2 or Innovus and Primetime, Tempus
Must have good communication and analytical skills.
Should be able to work closely with IP Design teams and Backend Physical Design teams across multiple sites.
Preferred
PhD in Computer Science, Electrical Engineering, or related field
Experience with memory compiler
Experience with formal equivalence - Cadence Conformal/Synopsys Formality
Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification
Experience with DFT and DFM flows
Benefits
Medical benefits
Financial benefits
Company
myGwork - LGBTQ+ Business Community
myGwork is the largest global platform for the LGBTQ+ business community.
Funding
Current Stage
Early StageTotal Funding
$4.77MKey Investors
24 HaymarketInnovate UK
2023-08-17Series Unknown· $1.66M
2023-08-17Grant· Undisclosed
2021-12-07Series A· $2.12M
Recent News
2024-04-10
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