Sr. Physical Design Engineer - Full Chip @ myGwork - LGBTQ+ Business Community | Jobright.ai
JOBSarrow
RecommendedLiked
0
Applied
0
Sr. Physical Design Engineer - Full Chip jobs in Sunnyvale, CA
Be an early applicantLess than 25 applicants
expire-info-iconThis job has closed.
company-logo

myGwork - LGBTQ+ Business Community · 2 days ago

Sr. Physical Design Engineer - Full Chip

Wonder how qualified you are to the job?

ftfMaximize your interview chances
Internet

Insider Connection @myGwork - LGBTQ+ Business Community

Discover valuable connections within the company who might provide insights and potential referrals, giving your job application an inside edge.

Responsibilities

Perform floorplanning, pin and feedthrough planning, repeater insertion, power grid generation and assembly of partitions.
Drive efficiency and quality improvements to the overall FC methodology including floorplan optimization for better utilization/QoR/runtime and timing and physical aware feedthrough/pin placement.
Coordinate collateral handoffs between the FC Design team and other functions within back-end design such as Clocking, Power Delivery and Partition synthesis/APR.
Drive physical design and timing closure including FEV, LVS, DRC, and reliability verification (IR drop / EM analysis).
Supervise and mentor other engineers.

Qualification

Find out how your skills align with this job's requirements. If anything seems off, you can easily click on the tags to select or unselect skills to reflect your actual expertise.

Semiconductor implementationScriptingAutomationChip front-endChip back-endFusion compilerDesign CompilerICC2InnovusPrimetimeTempusIP DesignPhysical DesignCommunicationAnalyticalTeamworkMemory CompilerFormal EquivalenceCadence ConformalSynopsys FormalityDesign ProcessRTL DesignFunctional VerificationDFTDFM Flows

Required

Bachelor's degree or higher in EE, CE, or CS
10+ years or more of practical semiconductor implementation experience
Scripting experience with Perl, Python, tcl, shell and drive to automate flows
Proficiency in chip front-end and back-end implementation tools such as Fusion compiler, Design Compiler, ICC2 or Innovus and Primetime, Tempus
Must have good communication and analytical skills.
Should be able to work closely with IP Design teams and Backend Physical Design teams across multiple sites.

Preferred

PhD in Computer Science, Electrical Engineering, or related field
Experience with memory compiler
Experience with formal equivalence - Cadence Conformal/Synopsys Formality
Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification
Experience with DFT and DFM flows

Benefits

Medical benefits
Financial benefits

Company

myGwork - LGBTQ+ Business Community

twittertwittertwitter
company-logo
myGwork is the largest global platform for the LGBTQ+ business community.

Funding

Current Stage
Early Stage
Total Funding
$4.77M
Key Investors
24 HaymarketInnovate UK
2023-08-17Series Unknown· $1.66M
2023-08-17Grant· Undisclosed
2021-12-07Series A· $2.12M

Leadership Team

leader-logo
Adrien Gaubert
Co-Founder & CMO
linkedin
Company data provided by crunchbase
logo

Orion

Your AI Copilot