149 applicants

Company

Original Job Post

AMD · 1 week ago

Physical Design Engineer

Santa Clara, CA

Full-time

Onsite

Senior Level

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Responsibilities

Own Physical design closure and PPA attainment for critical Graphics blocks

Tasks to include RTL Synthesis, Placement, Clock tree synthesis, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification and Sign Off

Work closely with RTL designers to analyze critical bottlenecks that impact PPA.

Identify complex technical problems, break them down, summarize multiple possible solutions, and lead the team in the right direction

Drive technical discussions with cross-functional teams (Including RTL design, CAD, and library teams) to explore optimizations to the design.

Technical lead of three to five senior-level engineers

Qualification

Find out how your skills align with this job's requirements. If anything seems off, you can easily click on the tags to select or unselect skills to reflect your actual expertise.

Physical designRTL synthesisPlacementClock tree synthesisOptimizationRoutingParasitic extractionStatic timing analysisIR drop analysisPhysical verificationSign offTechnical problem solvingOptimizationsTechnical leadershipCommunicationCollaborationAnalyticalProblem-solvingLeadershipAsic physical designRtl analysisTiming closurePhysical design closureTaping outSub 5nm designsCad toolsSynopsysCadenceMentor graphicsWorking experience

Required

Passion for pushing PPA on latest technology nodes and for Physical Design

Excellent communication skills and experience collaborating with other engineers located in different sites/timezones

Strong analytical and problem-solving skills

Willingness to learn and take on problems

Own Physical design closure and PPA attainment for critical Graphics blocks

Tasks to include RTL Synthesis, Placement, Clock tree synthesis, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification and Sign Off

Work closely with RTL designers to analyze critical bottlenecks that impact PPA

Identify complex technical problems, summarize multiple possible solutions, and lead the team in the right direction

Drive technical discussions with cross functional teams to explore optimizations to the design

Technical lead of three to five senior level engineers

Bachelors or Masters degree in computer engineering/Electrical Engineering

Preferred

ASIC Physical Design from RTL to GDSII

Excellent analytical and problem-solving skills along with attention to details

Strong background in RTL analysis, Timing and Physical Design closure

Hands-on experience in taping out sub 5nm designs

Expert knowledge and working experience on CAD tools from Synopsys, Cadence and Mentor Graphics

Strong communication, Time Management, and Presentation Skills

Must be a self-starter, and be able to independently and efficiently drive tasks to completion

Ability to provide mentorship and guidance to junior and senior engineers, and be an effective team player

Benefits

Discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan

Competitive benefits

Company

AMD

Glassdoor

4.1

Advanced Micro Devices (AMD) is a semiconductor company that designs and develops graphics units, processors, and media solutions.

Founded in 1969

Santa Clara, California, USA

10,001+ employees

http://www.amd.com

H1B Sponsorship

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2020 (559)