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Intel Corporation · 4 days ago
Physical Design Engineer - STA
Santa Clara, CA
Full-time
Hybrid
Senior Level
$162K/yr - $259K/yr
4+ years exp
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Insider Connection @Intel Corporation
Responsibilities
Performs timing analysis and timing optimization, generates, and verifies timing constraints, and fixes timing violations at chip/block level for SoCs.
Conducts timing rollups, designs for functionality, and develops performance and power optimized clock networks.
Develops and defines methodologies to ensure highest quality of timing models that enable the physical design team to operate efficiently.
Defines the right process, voltage, and temperature (PVT) conditions to be used for timing analysis for a given design based on the product plans such as operating conditions and binning.
Works closely with the clocking team and other backend full chip designers for clocking balance, timing fixes, power delivery, and partitioning.
Collaborates with architecture, clocking design, and logic design teams to deliver flow development for chip integration and validates high performance low power clock network guidelines.
Qualification
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Required
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science with 6+ years of relevant experience OR a Master's degree in Electrical Engineering, Computer Engineering, Computer Science with 4+ years of relevant experience OR PhD in Electrical Engineering, Computer Engineering, Computer Science with 2+ years of relevant experience
4+ years of experience in VLSI design, STA sign-off, constraint development
2+ years of experience programming in Perl or Python or Shell scripting, TCL
2+ years of experience supporting post silicon debug
2+ years of experience in EDA tools such as Cadence or Synopsys or Mentor Graphics
Preferred
Master's degree in Electrical Engineering, Computer Engineering, Computer Science with 6+ years of relevant experience OR PhD in Electrical Engineering, Computer Engineering, Computer Science with 4+ years of relevant experience
6+ years of experience with PrimeTime, Tempus
6+ years of experience defining STA sign-off criteria, methodology, constraints
6+ years of experience leading the execution to drive SoC STA closure for tape-out and supporting silicon debug
Benefits
Health
Retirement
Vacation
Company
Intel Corporation
Intel Corporation manufactures microprocessors for desktop and notebook PCs, servers, and workstations. It is a sub-organization of Intel.
10,001+ employees
H1B Sponsorship
Intel Corporation has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Trends of Total Sponsorships
2023 (2574)
2022 (4775)
2021 (3955)
2020 (1391)
Funding
Current Stage
Late StageLeadership Team
Robert H. Swan
CEO
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Chief Technology Officer - Network and Edge Group
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