Acceler8 Talent · 4 days ago

Principal Physical Design Engineer

Mountain View, CA

Full-time

Hybrid

Senior Level

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Responsibilities

Develop scalable solutions for silicon and physical design methodologies across blocks, subsystems, and full-chip designs.

Lead chip-level physical design tasks including floor-planning, placement, routing, optimizations, timing closure, and verification.

Conduct reviews and provide progress updates based on critical PPA metrics.

Collaborate closely with design, DFT (Design for Testability), and other key stakeholders.

Coordinate effectively with design services partners and third-party vendors on block-level and chip-level closure.

Qualification

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RTL to Silicon TransitionPhysical DesignASICsSOCsFloor PlanningRouteClock Tree InsertionTiming AnalysisPhysical VerificationElectrical Sign-offGDSDesign PartitioningPPATapeoutProject ManagementThird-party Design ServicesSubsystems

Required

Extensive experience transitioning RTL to silicon, driving physical design for subsystems and/or top-level functions within ASICs and SOCs, from early RTL design and netlist to production silicon.

Proven expertise in floor planning, place and route, clock tree insertion and analysis, timing analysis, physical verification, electrical sign-off, and related areas to prepare tapeout-ready GDS for large physical blocks and/or top-level designs.

Demonstrated project experience collaborating with design, verification, and DFT teams to optimize design partitioning for PPA and sign-off.

Experience in managing third-party design services partners, preferably involved in advancing subsystems and/or top-level designs from initial floor plan to sign-off and tapeout.