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Company

Original Job Post

Microsoft · 4 days ago

Senior Design Verification Engineer

North Carolina, United States

Full-time

Hybrid

Senior Level

$117K/yr - $229K/yr

7+ years exp

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Responsibilities

Define verification strategy, requirements, test environments for IP level verification.

Create testplans and write tests to provide complete features coverage.

Own verification for complex IPs, including creating testplans, developing Universal Verification Methodology (UVM) components and environments from scratch, writing test cases, debugging failures to root cause issues, running and maintaining regression suites, and closing coverage.

Develop and implement technical solutions to complex quality and design challenges.

Write scoreboards, sequences, constraints, assertions and functional coverage.

Write makefiles and scripts for verification infrastructure.

Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment.

Lead small teams of verification engineers and mentor engineers.

Collaborate with teams across sites and geographies.

Qualification

Find out how your skills align with this job's requirements. If anything seems off, you can easily click on the tags to select or unselect skills to reflect your actual expertise.

Verification MethodologySystem VerilogTest Plan DevelopmentFunctional CoverageVerification PrinciplesTestbenchesUVMCoverageAssertionsVerilogDebuggingCommunicationCollaborationTeamworkTechnical EngineeringElectrical EngineeringComputer EngineeringComputer Science

Required

7+ years of related technical engineering experience

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience

Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

10+ years of Technical Engineering Experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamental

Experience in test plan development to define test cases, checkers, assertions, and functional coverage points

Experience in verification of many designs at unit level

Knowledge of verification principles, testbenches, UVM, and coverage

Knowledge of system verilog class, constraints, coverage and assertions

Proficient communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams

Proficient in reading, debugging, and/or designing using Verilog languages

Preferred

11+ years technical engineering experience

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience

Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience

Company

Microsoft

Glassdoor

4.3

Microsoft is a software corporation that develops, manufactures, licenses, supports, and sells a range of software products and services.

Founded in 1975

Redmond, Washington, USA

10,001+ employees

https://www.microsoft.com

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