CCIT INC · 3 days ago

Senior Design Verification Engineer

United States

Full-time

Remote

Senior Level

10+ years exp

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Hiring Manager

Mohammad Zeeshan Sheikhzada

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Responsibilities

At-least 10+ years of experience in System Verilog HVL and C++/C

At-least 10+ year of experience in UVM.

Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure.

Proficient in SVTB/UVM, C++ testbench.

Understand DSP is a plus.

Subversion for Repository and Bugzilla is also a Plus.

Proficient in debug and assertions coding.

Verification closure with team.

Make/Perl/Python / any script.

Any protocol experience is fine.

Ensure customer satisfaction.

Reporting to customer on daily or weekly progress effectively.

Qualification

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System Verilog HVLC++/CUVMBFMDriverScoreboardSVTBAssertionsMakePerlPythonScriptingEthernetTestplanCoverage PlanTestcasesSubsystem VerificationSystem VerificationUnderstand DSPSubversionBugzillaProblem-solving