Apple · 3 days ago

PLL Design Engineer

Cupertino, CA

Full-time

Onsite

Senior Level

$139K/yr - $256K/yr

3+ years exp

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Comp. & Benefits

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Responsibilities

Understand system level requirements to create overall PLL specifications.

Create behavioral models of PLL to drive architectural decisions and derive block-level requirements for analog and digital blocks.

Work closely with mask design team to implement layout view of designs.

Complete top-level spice and mixed-mode simulations to validate top-level integration.

Run pre-tapeout verification flows to confirm design meets performance, power, reliability and timing requirements.

Define production/bench-level test plans for post-silicon characterization.

Work with lab engineers in taking lab measurements to validate IP.

Review ATE and lab test results to resolve yield issues and drive bug fixes.

Work with system teams in system bringup and debug.

Hold design reviews of blocks with peers/management to show design meets spec targets and requirements.

Qualification

Find out how your skills align with this job's requirements. If anything seems off, you can easily click on the tags to select or unselect skills to reflect your actual expertise.

BSEESystem Level RequirementsPLL SpecificationsBehavioral ModelsAnalogDigital BlocksMask DesignLayout ViewSpice SimulationsMixed-Mode SimulationsPre-Tapeout VerificationPerformance AnalysisPower AnalysisReliability AnalysisTiming AnalysisTest PlansPost-Silicon CharacterizationLab MeasurementsATELab Test ResultsYield IssuesBug FixesSystem BringupDebuggingDesign Reviews

Required

BSEE with minimum 3+ years of industry experience