Acceler8 Talent · 4 days ago

Principal Physical Design Engineer

Mountain View, CA

Full-time

Onsite

Senior Level

$250K/yr - $300K/yr

8+ years exp

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Drew Cummings

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Responsibilities

You will develop and enhance silicon design and physical design methodologies, creating scalable solutions for blocks, subsystems, and full chip designs from RTL to GDS.

You will take ownership of entire subsystems or specific subsets and chip-level physical design tasks, including floor-planning, placement, clock insertion, routing, optimization, timing closure analysis, physical verification closure, and electrical analysis.

You will plan and lead intermediate and final reviews, as well as track execution progress using key PPA metrics, ensuring milestones such as design freeze and tapeout are met.

You will collaborate closely with design, DFT, and other physical design team members to achieve top-tier performance, power, and area results for the subsystem or block.

You will coordinate with design services partners and critical third-party vendors to plan and execute block-level and chip-level closure for the blocks you manage and oversee.

Qualification

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ASIC Physical DesignFloorplanningRouteClock Tree InsertionTiming AnalysisPhysical VerificationElectrical Sign-offDesign PartitioningPPADesign ServicesSubsystem DesignFloor PlanSign-OffTapeout

Required

Minimum 8 years of industry experience in ASIC Physical Design

Proven track record in floorplanning, place and route, clock tree insertion and analysis, timing analysis, physical verification, electrical sign-off, and related areas, ensuring tapeout-ready GDS for large physical blocks and/or top-level designs

Demonstrated ability to collaborate with design, verification, and DFT teams to structure and partition designs optimally for PPA and sign-off

Preferred

Experience working with third-party design services partners, taking subsystems and/or top-level designs from initial floor plan to sign-off and tapeout is a plus