Design Verification Engineer @ Kaygen, Inc. | Jobright.ai
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Design Verification Engineer jobs in San Jose, CAH1B Visa Sponsored Design Verification Engineer jobs in San Jose, CA
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Kaygen, Inc. ยท 2 days ago

Design Verification Engineer

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Hiring Manager
Chandrashekar C
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Responsibilities

Architecture Design: Architect block and full-chip verification environments using Hardware Verification Languages (HVLs) and constrained random techniques.
Test Development: Develop comprehensive test plans and coverage metrics based on design specifications. Write block-level and chip-level tests using C, System Verilog (SV), and UVM.
Simulation and Debugging: Debug RTL (Register Transfer Level) and Gate-level simulations to identify and resolve issues. Collaborate with design engineers to verify and validate fixes.
Bug Replication and Validation: Replicate silicon bugs in simulation environments and validate fixes or software workarounds.
ATE Vector Bringup Support: Convert verification tests into test patterns suitable for Automatic Test Equipment (ATE). Assist Test Engineers in the setup and validation of ATE vectors.
Methodology Evaluation and Automation: Stay updated with the latest verification methodologies and tools. Develop scripts and automation flows to streamline verification processes.

Qualification

Find out how your skills align with this job's requirements. If anything seems off, you can easily click on the tags to select or unselect skills to reflect your actual expertise.

System VerilogUVMConstrained Random VerificationSOC ArchitecturesEmbedded CPUsMixed Signal InterfacesTest Plan DevelopmentCoverage MetricsVerification TestsRTL DebuggingGate-level SimulationsATE Vector BringupTest Pattern ConversionSOC Design VerificationIndustry Tools KnowledgeScripting PythonScripting PerlAnalyticalProblem-SolvingCollaborative

Required

Proficiency in HVLs such as System Verilog and methodologies like UVM.
Experience with constrained random verification techniques.
Strong understanding of SOC architectures, embedded CPUs, and mixed signal interfaces.
Ability to develop test plans, coverage metrics, and verification tests.
Expertise in debugging RTL and Gate-level simulations.
Familiarity with ATE vector bringup and test pattern conversion.

Preferred

Prior experience in verifying complex SOC designs.
Knowledge of industry-standard tools and methodologies for verification.
Strong analytical and problem-solving skills.
Ability to work effectively in a collaborative team environment.
Scripting skills for automation (e.g., Python, Perl) are desirable.

Company

Kaygen, Inc.

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Kaygen, an award-winning technology consulting and talent firm, assists organizations to achieve digital transformation.

H1B Sponsorship

Kaygen, Inc. has a track record of offering H1B sponsorships. Please note that this does not guarantee sponsorship for this specific role. Below presents additional info for your reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Trends of Total Sponsorships
2023 (2)
2022 (2)
2021 (8)
2020 (16)

Funding

Current Stage
Growth Stage

Leadership Team

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Anshul Chaturvedi
Founder & CEO
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Rashmi Chaturvedi
Co-Founder & President
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Company data provided by crunchbase
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