75 applicants
SpanIdea Systems ยท 2 days ago
Senior Static Timing Analysis (STA) Engineer
San Jose, CA
Full-time
Onsite
Senior Level
$90/hr - $115/hr
10+ years exp
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Responsibilities
Conduct static timing analysis (STA) and optimize timing for System on Chips (SoCs) at full chip and block levels.
Generate and validate timing constraints, conduct Signal Integrity (SI)/Noise analysis, and resolve timing and noise issues.
Utilize Synopsys timing analysis tool Primetime and other relevant tools in timing ecosystems.
Apply scripting languages such as TCL, Perl, or Python for automation purposes.
Demonstrate a solid understanding of ASIC design flow, covering front-end and back-end processes.
Qualification
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Required
A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a closely related field is required.
Experience with Static Timing Analysis/STA: 10 years (Required)
Experience with Physical Design Engineering: 10 years (Required)
Ability to Commute to San Jose, CA (Required)
Preferred
Familiarity with scripting languages such as TCL, Perl, or Python for automation purposes is desired.
Experience with low-power design methodologies is advantageous.
Familiarity with analog and mixed-signal design principles is advantageous for specific positions.
Benefits
Dental insurance
Health insurance
Vision insurance
Company
SpanIdea Systems
Spanidea Systems is a global leader in technology design and system engineering at the forefront of innovation.
501-1,000 employees
Funding
Current Stage
Late StageRecent News
Company data provided by crunchbase
