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Company

Original Job Post

Astera Labs · 3 days ago

Staff Semiconductor Packaging Engineer

Santa Clara, CA

Full-time

Onsite

Senior Level

5+ years exp

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Responsibilities

Manage package engineering tasks throughout the product lifecycle.

Collaborate with chip and package design, manufacturing, and hardware engineering teams to meet program goals.

Utilize expertise in signal and power integrity to optimize package and system-level performance.

Independently drive package development from concept to production in the NPI cycle.

Perform system-level analysis for package optimization and tape-out.

Drive chip + package + PCB simulation, optimization, and sign-off using circuit and system level analysis tools.

Refine modeling methodology and flow to ensure real-world performance matches design expectations.

Work directly with substrate suppliers and OSAT vendors in the package development cycle.

Qualification

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Packaging SI/PI AnalysisOptimizationInterconnectionsANSYS 3DLayoutHFSSSIwaveSystem-Level AnalysisTape-OutNPI CycleFCBGA Package SI ModelsSPICEPDN AnalysisDCIRPower TreeLoop InductanceTarget ImpedanceAC Time Domain AnalysisKeysight ADSChip + Package + PCB SimulationERLEye-DiagramTransient ResponseSI/PI Optimization TechniquesHigh-Speed Industry ProtocolsPCIeSERDESEthernetDDRCXLSimulation-to-Measurement Correlation Analysis

Required

MS/PhD in Electrical Engineering

A minimum of 5 years of experience in packaging SI/PI analysis and optimization, encompassing interconnections at various levels (chip, package, and PCB)

Hands-on experience in using package and PCB extraction tools such as ANSYS 3DLayout, HFSS or SIwave and developing complete SI/PI models and performing system-level analysis for package optimization and tape-out

Experience of independently driving package development from concept to production in the NPI cycle by working cross-functionally with both internal teams and external suppliers

Entrepreneurial, open-minded behavior and hands-on work ethic with the ability to prioritize a dynamic list of multiple tasks. Working with minimal guidance and supervision to deliver solutions

Experience of extracting FCBGA package SI models such as s-parameter and SPICE

Experience of performing complete PDN analysis such as DCIR, power tree, loop inductance, target impedance and AC time domain analysis

Experience of using circuit and system level analysis tools (such as Keysight ADS) to drive chip + package + PCB simulation, optimization and sign-off (ERL, eye-diagram, transient response, etc.)

Deep knowledge of industry best known design method and commonly used SI/PI optimization techniques

Working knowledge of typical high-speed industry protocols such as PCIe, SERDES, Ethernet, DDR, CXL, etc

Able to perform simulation-to-measurement correlation analysis, and refine modeling methodology and flow, to ensure real-world performance match design expectations

Understanding of FCCSP and FCBGA packages from perspectives of electrical performance, material characteristics, manufacturing, BOM, supply chain, reliability, risk management and failure analysis

Experience of working directly with substrate suppliers and OSAT vendors in package development cycle

Preferred

Allegro Package Designer (APD) experience to view, edit or verify designs for optimization iterations and package sign-off

Experience of DDR channel simulation analysis is a plus

Experience with electrical measurement equipment such as VNA, oscilloscope, and TDR is a plus

Company

Astera Labs

Astera Labs is a semiconductor company that provides connectivity solutions for intelligent systems.

Founded in 2017

Santa Clara, California, USA

201-500 employees

https://www.asteralabs.com

H1B Sponsorship

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