42 applicants

Company

Original Job Post

Synopsys Inc · 3 days ago

Staff RTL Design Engineer

Mountain View, CA

Full-time

Onsite

Senior Level

$122K/yr - $188K/yr

5+ years exp

Wonder how qualified you are to the job?

Maximize your interview chances

Electronic Design Automation (EDA)Information Services

H1B Sponsorship

Insider Connection @Synopsys Inc

Discover valuable connections within the company who might provide insights and potential referrals, giving your job application an inside edge.

Responsibilities

Working closely with architects to develop micro-architecture and hardware specifications for the design blocks for ARC-V processor IP.

Developing RTL code for the design blocks with PPA considerations

Carrying out Linting, CDC, RDC, Synthesis and Timing Analysis of design blocks

Work closely with verification team to review test plans and setting the sign-off criteria for the design and verification activities

Interact and collaborate with various stake holders in the project (in areas related to Verification, SW, DFT, Physical design, Prototyping.. etc)

Qualification

Find out how your skills align with this job's requirements. If anything seems off, you can easily click on the tags to select or unselect skills to reflect your actual expertise.

ASIC Digital DesignCPU ArchitecturesRISC-VHigh Performance Design TechniquesLow Power Design TechniquesDigital Design FundamentalsVerilogSystem VerilogDebuggingDVEVerdiSpyglassDesign CompilerTCMFishtailScriptingPerlPythonJavaScriptGitRevision ControlTeam OrientedClear CommunicationProblem SolvingIP ArchitectureProcess TechnologiesCPU DebuggingAutomotive Safety StandardsASIL

Required

Bachelors of Science in Computer, Electrical Engineering or similar

5+ years experience in ASIC digital design domain

Or Master of Science in Computer, Electrical Engineering or similar

3+ years experience in ASIC digital design domain

Team oriented person with clear verbal and written communication

Exposure to CPU/processor architectures; RISC-V experience highly desirable

Knowledge of design techniques for high performance and low power

Must have strong digital design fundamentals

Hands-on expertise with Verilog, System Verilog

Hands-on expertise with debugging failed scenarios using DVE/Verdi

Hands-on expertise with Spyglass, Design Compiler, TCM/Fishtail

Experience in developing scripts using Perl, Python, Javascript or similar languages

Excellent debug and problem solving skills

Experience with git or other revision control environments

Preferred

Cutting edge experience in IP architecture and design, utilizing the latest process technologies

Hands-on expertise debugging CPU designs is highly desirable

Exposure to automotive safety (ASIL) standards is an advantage

Benefits

Health, wellness, and financial benefits

Annual bonus

Equity

Other discretionary bonuses

Company

Synopsys Inc

Glassdoor

4.0

Catalyzing the era of pervasive intelligence, Synopsys delivers trusted and comprehensive silicon to systems design solutions, from electronic design automation to silicon IP and system verification and validation.

Founded in 1986

Mountain View, California, USA

10,001+ employees

http://www.synopsys.com

H1B Sponsorship

Synopsys Inc has a track record of offering H1B sponsorships. Please note that this does not guarantee sponsorship for this specific role. Below presents additional info for your reference. (Data Powered by US Department of Labor)

Distribution of Different Job Fields Receiving Sponsorship

Trends of Total Sponsorships

2023 (121)

2022 (207)

2021 (227)

2020 (193)