104 applicants

This job has closed.

Company

Original Job Post

Apple · 3 days ago

Digital Integration & Timing Engineer

Sunnyvale, CA

Full-time

Onsite

Mid Level

$139K/yr - $256K/yr

3+ years exp

Wonder how qualified you are to the job?

Maximize your interview chances

Consumer ElectronicsHardware

H1B Sponsorship

Comp. & Benefits

Insider Connection @Apple

Discover valuable connections within the company who might provide insights and potential referrals, giving your job application an inside edge.

Responsibilities

Full chip and block-level timing constraint and closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation).

Deploy and enhance methodology and flows related to timing constraint verification and timing closure.

Generation of consistent block and full chip timing constraints.

Support digital chip integration work and flows.

Execute low power design and physical synthesis techniques, deploying knowledge of UPF and power intent verification.

Collaborate with Chip Architecture, Design Verification, Physical Design, DFT, and power teams to achieve the tape out success on designs - generally bridging everything between the RTL and PD worlds.

Qualification

Find out how your skills align with this job's requirements. If anything seems off, you can easily click on the tags to select or unselect skills to reflect your actual expertise.

ASIC design flowSTA toolsUPF usageTiming constraintsTiming cornersSignal integrityScripting languagesLogic synthesisPPA techniquesDesign CompilerFusion CompilerGenusLogic equivalenceFunctional ECOsDFT methodologiesRTL VerilogVHDLDigital top integrationTool automationAPIsEDA tools

Required

BS and 3+ years of relevant industry experience.

Knowledge of the entire ASIC design flow from RTL integration through synthesis, static timing analysis, scripting, P&R to tapeout.

Expertise in STA tools and flow.

UPF usage for power and voltage islands.

Hands-on experience in timing/SDC constraints generation and management.

Knowledge of timing corners, operating modes, process variations, and signal integrity-related issues.

Proficient in scripting languages (TCL and PERL).

Logic synthesis execution for efficient PPA using physically aware techniques in single-digit process nodes using Design Compiler, Fusion Compiler &/or Genus.

Proficient in the closure of end-to-end logic equivalence (FV, LEC) with functional ECOs in the mix.

Familiarity with DFT and backend related methodologies and tools.

Proficient with RTL Verilog/VHDL.

Knowledge of digital top integration flows/methodology/checks.

Experience with script-based tool automation, API’s and scripting languages for EDA tools, such as; Design Compiler, Genus, PrimeTime, etc.

Benefits

Comprehensive medical and dental coverage

Retirement benefits

Discounted products and free services

Reimbursement for certain educational expenses

Discretionary bonuses or commission payments

Relocation assistance

Company

Apple

Glassdoor

4.2

Apple is a corporation that designs, manufactures, and markets consumer electronics, personal computers, and software.

Founded in 1976

Cupertino, California, USA

10,001+ employees

http://www.apple.com

H1B Sponsorship

Apple has a track record of offering H1B sponsorships. Please note that this does not guarantee sponsorship for this specific role. Below presents additional info for your reference. (Data Powered by US Department of Labor)

Distribution of Different Job Fields Receiving Sponsorship

Trends of Total Sponsorships

2023 (2569)

2022 (4857)

2021 (4908)

2020 (3580)