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Company

Original Job Post

Astera Labs · 2 days ago

Senior Physical Design Engineer

Santa Clara, CA

Full-time

Hybrid

Senior Level

10+ years exp

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Responsibilities

Hands-on and thorough knowledge of synthesis, place and route, timing, extraction and other backend tools and methodologies for technologies 16nm or less.

Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level.

Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production.

Experience with Cadence and/or Synopsys physical design tools/flows.

Familiarity and working knowledge of System Verilog/Verilog.

Experience with DFT tools and techniques.

Experience in working with IP vendors for both RTL and hard-mac blocks.

Good scripting skills in python or Perl.

Good knowledge of design for test (DFT), stuck-at and transition scan test insertion.

Familiarity with DFT test coverage and debug.

Familiarity with ECO methodologies and tools.

Qualification

Find out how your skills align with this job's requirements. If anything seems off, you can easily click on the tags to select or unselect skills to reflect your actual expertise.

Electrical engineeringSoC/silicon productsServerStorageNetworking applicationsRouteTiming closureBackend toolsMethodologies16nm technologyFormal verificationFull-chip ownershipArchitectureGDSIICadence toolsSynopsys toolsSystem VerilogVerilogDFT toolsIP vendorsRTLHard-mac blocksPythonPerlProblem-solvingProfessionalismPrioritizationIndependenceEntrepreneurial mindsetOpen-mindedness

Required

Strong academic and technical background in electrical engineering

Bachelor’s degree in EE

≥10 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications

Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision

Entrepreneurial, open-mind behavior and can-do attitude

Hands-on and thorough knowledge of synthesis, place and route, timing, extraction and other backend tools and methodologies for technologies 16nm or less

Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level

Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production

Experience with Cadence and/or Synopsys physical design tools/flows

Familiarity and working knowledge of System Verilog/Verilog

Experience with DFT tools and techniques

Experience in working with IP vendors for both RTL and hard-mac blocks

Good scripting skills in python or Perl

Preferred

Master’s degree in EE

Good knowledge of design for test (DFT), stuck-at and transition scan test insertion

Familiarity with DFT test coverage and debug

Familiarity with ECO methodologies and tools

Company

Astera Labs

Astera Labs is a semiconductor company that provides connectivity solutions for intelligent systems.

Founded in 2017

Santa Clara, California, USA

201-500 employees

https://www.asteralabs.com

H1B Sponsorship

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Trends of Total Sponsorships

2023 (12)

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2020 (13)