BrickRed Systems · 2 days ago
Mask Layout Design Engineer - REMOTE
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Responsibilities
Execute IC layout for high-performance CMOS Interface D2D and SERDES in 2nm and 3nm CMOS process nodes.
Utilize Cadence Virtuoso for analog IP layouts such as PLLs, ADCs, RX, TX, OTAs, LDO, and Clock Distribution .
Conduct layout design reviews , floor-planning , LVS, DRC, and DFM .
Qualification
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Required
0-2 years of experience in high-performance analog layout; FINFET CMOS process preferred.
Strong knowledge of EDA tools (Cadence, Mentor, Synopsys).
Familiarity with analog blocks layout (e.g., VCOs, charge pumps, PLLs, ADCs).
Skills in floor planning, block-level routing, and high-speed IO design.
Proficiency in advanced layout techniques like matching, symmetrical layout, and signal shielding.
Preferred
2 years’ experience in FINFET CMOS process for high-performance analog layout (2nm and 3nm preferred).
2 years’ experience with Cadence, Mentor, Synopsys EDA tools.
2 years’ experience in layout of analog blocks (VCOs, PLLs, ADCs, RX/TX).
Company
BrickRed Systems
BrickRed Systems is an IT Consulting firm specializes in business intelligence, technology consulting, security consulting & more.
H1B Sponsorship
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Trends of Total Sponsorships
2023 (1)
2022 (1)
2020 (1)
Funding
Current Stage
Late StageCompany data provided by crunchbase