Senior ASIC Design Verification Engineer jobs in United States
cer-icon
Apply on Employer Site
company-logo

Ethernovia · 5 months ago

Senior ASIC Design Verification Engineer

Ethernovia is fundamentally changing how cars of the future are built by unifying in-vehicle networks into an end-to-end Ethernet system. As a Senior ASIC Design Verification Engineer, you will be responsible for all aspects of digital SoC verification and work with various teams to ensure the validation of advanced automotive communication semiconductors.

Autonomous VehiclesInformation and Communications Technology (ICT)Network HardwareSoftware
badNo H1BnoteU.S. Citizen Onlynote

Responsibilities

Responsible for all aspects of digital SoC verification
Work with architects, designers, and SW engineers to plan and execute verification and validation of advanced automotive communication semiconductors and systems
Contribute to a positive, trusting, and cohesive working environment based on integrity and strong work ethics

Qualification

ASIC verification experienceVerilog/System VerilogUVMPythonC/C++Debugging simulation failuresNetworking protocolsAttention to detailsCommunicationCollaboration skills

Required

BS and/or MS in Electrical Engineering, Computer Science, or related field
Minimum 10+ years of ASIC verification experience
Strong understanding of ASIC verification fundamentals and industry standard methodologies
Experience with Verilog/System Verilog, UVM, Python, TCL, C/C++
Experience with the full verification flow, from spec to coverage analysis to gate level sim
Debugging failures in simulation to root cause problems
Self-motivated and able to work effectively both independently and in a team
Excellent communication/documentation skills
Attention to details
Collaboration across multidisciplinary and international teams

Preferred

Experience in any of the following areas: Networking (Ethernet MAC, PHY, Switching, TCP/IP, security, PCIe and other industry standard protocols)
Video standards, protocols, processing
Digital signal processing filters
Third party IP (SerDes, controllers, processors, etc.)
Modular and Reusable Testbench architecture
Design for re-use of pre and post silicon tests and infrastructure
Automation of testbench creation, tests, regression, or EDA tools
Knowledge of SystemC and/or DPI

Benefits

Pre IPO stock options
Cutting edge technology
World class team
Competitive base salary
Flexible hours
Medical, dental and vision insurance for employees
Flexible vacation time to promote a healthy work-life balance

Company

Ethernovia

twittertwitter
company-logo
Ethernovia is a developer of an Ethernet system that provides the next evolution in vehicle communication.

Funding

Current Stage
Growth Stage
Total Funding
$64M
2023-05-15Series A· $64M
2021-10-20Series A

Leadership Team

leader-logo
Darren Engelkemier
VP Silicon Engineering, Co-Founder
linkedin
leader-logo
Hossein Sedarat
Chief Technology Officer, Co-Founder
linkedin
Company data provided by crunchbase