Capgemini Engineering · 1 day ago
RTL Design Engineer
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Responsibilities
Develop micro architectural document from requirements specifications.
Extensive RTL design utilizing Verilog / SystemVerilog
Perform basic linting and other QC
Collaborate and support SoC integration as needed
Qualification
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Required
Minimum 10 years of strong experience in Digital design at RTL level using Verilog / SystemVerilog
Experience developing micro architectural document from requirements specifications.
Conceptual Design experience, this is not SoC integration of blocks.
Experience applying linting and other (QC) quality checking and basic verification of designs.
Well versed in SystemVerilog Language
EDA tools Cadence and Synopsys
Strong communication and collaboration skills
Experienced with designs related to Video, AR, VR or MR.
IP Design – similar memory controllers, Image processing IP /Design and interconnect
Preferred
DMA, memory controller, MIPI protocols communication
DSI/CSI, data and control path pipeline design, interconnect and AMBA interfaces.
RTL Design automation, using Python scripting.
Benefits
Flexible work
Healthcare including dental, vision, mental health, and well-being programs
Financial well-being programs such as 401(k) and Employee Share Ownership Plan
Paid time off and paid holidays
Paid parental leave
Family building benefits like adoption assistance, surrogacy, and cryopreservation
Social well-being benefits like subsidized back-up child/elder care and tutoring
Mentoring, coaching and learning programs
Employee Resource Groups
Disaster Relief
Company
Capgemini Engineering
Capgemini Engineering is a global innovation and engineering consulting firm.
Funding
Current Stage
Public CompanyTotal Funding
$4M2019-06-24Acquired· by Capgemini ($4.1B)
2006-09-19Post Ipo Equity· $4M
1990-01-05IPO· epa:ALT
Leadership Team
Recent News
2024-04-29
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