Be an early applicantLess than 25 applicants

Company

Tessolve · 8 hours ago

Physical Design Engineer

Austin, TX

Contract

Remote

Senior Level, Lead/Staff

10+ years exp

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ManufacturingSemiconductor

Hiring Manager

Amrit Anshuman Swain

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Responsibilities

Experience: 10yrs+

Synopsys Fusion Compiler/ICC2 (Synthesis, DFT insertion, Place & Route, Chip Finishing, PT-SI STA, Timing Closure, PV (DRC/ERC/PERC/LVS)

Synopsys DC, DCG, DC TOPO

Synopsys Flow Development & SOC implementation methodologies that will be deployed and used by our Synopsys customer Physical Design Implementation team members

Familiar with Synopsys Lynx a plus

RTL Hand-over experience a plus for RTL to GDS

Experience with top-level floorplanning, bump-maps, RDL IO Pad/Ring creation/verification, power grid creation/verification, hierarchal floorplanning/partitioning

Solid experience with full SOC clocking methodologies (H-Tree, Structure Clocking, MS CTS for Top/Blocks with push/down & bottoms up approaches)

Highly proficient with SDC STA constraints development driving back-end tools for blocks and full-chip through timing closure & sign-off

Ability to define sign-off requirements/margins based on Foundry technology requirements a plus

DFT experience with compression, scan, TDF, and MEMBIST a plus

Synopsys Formality for formal verification (RTL to Gate, Gate-to-Gate) & Formality ECO flows

Familiar with UPF flows & methodologies for multi-voltage power domains with turn on/turn off using UPF

Synopsys ICV for PV (Physical Verification – DRC/ERC/LVS/PERC)

Ansys Redhawk SC (For IR analysis for static, dynamic, & EMIR)

Experience in PD implementation/design closure on complex IP Sub-Systems such as PCIe, USB, MIPI, DDR, & HBM a plus

Experience with GlobalFoundries, TSMC, & Samsung technology nodes are a plus

Consultants should have a solid track record on execution delivering to high-quality standards for delivering to high quality tape-out

Qualification

Find out how your skills align with this job's requirements. If anything seems off, you can easily click on the tags to select or unselect skills to reflect your actual expertise.

Synopsys Fusion CompilerICC2DFT insertionPlace & RouteTiming ClosureSynopsys DCSOC implementation methodologiesTop-level floorplanningFull SOC clocking methodologiesSDC STA constraints developmentSynopsys FormalitySynopsys ICVAnsys Redhawk SCPD implementation/design closureRTL Hand-overBump-mapsRDL IO Pad/Ring creationPower grid creationHierarchal floorplanningSign-off requirementsDFT experienceUPF flowsGlobalFoundries technology nodesTSMC technology nodesSamsung technology nodes

Required

Experience: 10yrs+

Synopsys Fusion Compiler/ICC2 (Synthesis, DFT insertion, Place & Route, Chip Finishing, PT-SI STA, Timing Closure, PV (DRC/ERC/PERC/LVS)

Synopsys DC, DCG, DC TOPO

Synopsys Flow Development & SOC implementation methodologies that will be deployed and used by our Synopsys customer Physical Design Implementation team members

Solid experience with full SOC clocking methodologies (H-Tree, Structure Clocking, MS CTS for Top/Blocks with push/down & bottoms up approaches)

Highly proficient with SDC STA constraints development driving back-end tools for blocks and full-chip through timing closure & sign-off

Ability to define sign-off requirements/margins based on Foundry technology requirements

Synopsys Formality for formal verification (RTL to Gate, Gate-to-Gate) & Formality ECO flows

Synopsys ICV for PV (Physical Verification – DRC/ERC/LVS/PERC)

Ansys Redhawk SC (For IR analysis for static, dynamic, & EMIR)

Consultants should have a solid track record on execution delivering to high-quality standards for delivering to high quality tape-out

Preferred

Familiar with Synopsys Lynx

RTL Hand-over experience a plus for RTL to GDS

Experience with top-level floorplanning, bump-maps, RDL IO Pad/Ring creation/verification, power grid creation/verification, hierarchal floorplanning/partitioning

DFT experience with compression, scan, TDF, and MEMBIST a plus

Familiar with UPF flows & methodologies for multi-voltage power domains with turn on/turn off using UPF

Experience in PD implementation/design closure on complex IP Sub-Systems such as PCIe, USB, MIPI, DDR, & HBM a plus

Experience with GlobalFoundries, TSMC, & Samsung technology nodes are a plus

Company

Tessolve

Glassdoor

3.8

Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, and spec to the product.

Founded in 1993

Bangalore, Karnataka, IND

1,001-5,000 employees