Akkodis · 18 hours ago
FPGA/ASIC Verification Engineer
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Responsibilities
As a FPGA/ASIC Design Verification Engineer, you will own functional verification for a custom controller.
You will develop functional verification infrastructure to ensure functional correctness of a design as well as improve the throughput of the verification effort.
In this role, you will develop test plans for functional units and subsystems.
You will analyze coverage from various dimensions and develop monitors and checkers for better quality assurance.
In the final stages, you will also run GLS related simulations.
UVM/python test development for driving VIPs and other stimulus drivers.
Generation of test components such as monitors, scoreboards and python models.
Coverage closure and GLS bringup and testing.
Qualification
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Required
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with verification methodologies and languages such as UVM and System Verilog.
Experience developing and maintaining verification testbenches, test cases, and test environments.
Experience in all aspects of verification life cycle, specifically, SDF and GLS simulations.
Experience in ethernet and SPI required.
Preferred
Master’s degree in Electrical Engineering, Computer Science, or related field.
UVM/System verilog experience 5+ years (10 + years preferred).
High proficiency in python.
Knowledge of general-purpose operating systems such as Linux and Android.
Experience in assertions and formal verification preferred.
Experience in ethernet, SPI, AXI, JTAG preferred.
Experience in analog and real number modelling preferred.
Benefits
Medical
Dental
Vision
Life insurance
Short-term disability
Additional voluntary benefits
An EAP program
Commuter benefits
401K plan
Paid Sick Leave
Holiday pay
Company
Akkodis
Akkodis is a digital engineering company and Smart Industry leader.
Funding
Current Stage
Late StageLeadership Team
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