Neuralink · 20 hours ago
Physical Design and Verification Engineer
Fremont, CA
Full-time
Onsite
Senior Level
$158K/yr - $243K/yr
5+ years expNeuralink is creating devices that enable a bi-directional interface with the brain, aiming to restore movement and sight while revolutionizing human interaction with digital worlds. The Physical Design and Verification Engineer will focus on RTL to GDSII Physical Design Implementation, including various aspects of synthesis and optimization, as well as physical signoff verification.
BiotechnologyMedicalNeuroscienceRobotics
Responsibilities
The Physical Design and Verification Engineer will be responsible for RTL to GDSII Physical Design Implementation, including Synthesis, Placement, Clock Tree Synthesis, Detailed Routing and Optimization, in addition to Physical Signoff Verification
Qualification
Required
Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience
Minimum 5 years of experience in digital physical design and verification
Excellence in complete RTL to GDSII flow with strong experience in the usage of industry-standard Electronic Design Automation (EDA) tools for both physical design and timing signoff
Deep knowledge on industry standards and practices in physical design including physically-aware synthesis flow, floor-planning, and place & route, metal fill, chip finishing, signal integrity checks, and dynamic EMIR-Drop analysis, and formal ESD verification
Experience in Signoff ECO flow to fix timing, noise, IR-Drop and EMIR violations
Experience in physical design verification to debug LVS/DRC/PERC issues at the chip/block level using industry standard tools
Experience in developing automation flow and scripts using Python, Perl, Makefile, Tcl and UNIX shell
Preferred
Master of Science (M.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience
Experience working on physical design and implementation of complex ASIC systems at advanced technology nodes, preferably 16nm and below
Experience in DFT (Design For Test) flows and ATPG
Experience in I/O design flow in multi-voltage power domain
Experience in building chip floor-plan including pin placement, partitions and power grid
Experience in hierarchical synthesis, place-and-route and design closure to meet timing, area, and UPF-driven low power constraints
Experience with build tools such as CMake and Bazel
Experience with code coverage and regression setup
Benefits
An opportunity to change the world and work with some of the smartest and most talented experts from different fields
Growth potential; we rapidly advance team members who have an outsized impact
Excellent medical, dental, and vision insurance through a PPO plan
Paid holidays
Commuter benefits
Meals provided
Equity (RSUs) Temporary Employees & Interns excluded
401(k) plan Interns initially excluded until they work 1,000 hours
Parental leave Temporary Employees & Interns excluded
Flexible time off Temporary Employees & Interns excluded
Company
Neuralink
Neuralink is a neurotechnology company that focuses on developing brain-computer interfaces designed to treat neurological disorders.
201-500 employees
H1B Sponsorship
Neuralink has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (11)
2024 (14)
2023 (7)
2022 (5)
2021 (7)
2020 (6)
Funding
Current Stage
Late StageTotal Funding
$1.34BKey Investors
CoreNest CapitalFounders FundVy Capital
2025-07-07Series Unknown
2025-06-17Secondary Market
2025-05-27Series E· $649M
Leadership Team
Dongjin Seo
Co-Founder, President & COO
Shivon Zilis
Director of Operations and Special Projects
Recent News
2026-01-09
Company data provided by crunchbase