Randstad Global Capability Center · 6 hours ago
Silicon Verification Engineer
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Responsibilities
Define, document, and implement a UVM verification environment including agents and scoreboards
Write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral
Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes
Support post-silicon verification activities of the products working with design and product teams
Qualification
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Required
US Citizen or Permanent Resident
1-3 overall years of experience in the field
Strong grasp of SystemVerilog and UVM
Minimum 3 years experience with SystemVerilog and UVM
Minimum 2 years experience with coding functional coverage (based off of SystemVerilog)
Minimum 2 years experience with scripting in either Python, Ruby, or C++
Minimum 1 years experience of exposure to formal methodology
Proficient in using Verilog and VMM/OVM/UVM
Experience in pre and post silicon verification test flow and automated test benches
Effective communication, collaboration, and teamwork skills
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related degree required
0-2 years of relevant experience required
Preferred
Bachelor’s degree in Electrical Engineering or a related field
Company
Randstad Global Capability Center
Randstad Global Capability Center (previously known as Randstad Offshore Services) is dedicated to helping Randstad become a best-in-class business services provider across the globe.
Funding
Current Stage
Late StageCompany data provided by crunchbase