Silicon Verification Engineer @ AllSTEM Connections | Jobright.ai
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Silicon Verification Engineer jobs in United States
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AllSTEM Connections · 8 hours ago

Silicon Verification Engineer

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Responsibilities

Define, document, and implement a UVM verification environment including agents and scoreboards
Write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral
Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes
Support post-silicon verification activities of the products working with design and product teams

Qualification

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SystemVerilogUVMFunctional coveragePythonRubyC++VerilogPrePost silicon verificationAutomated test benchesFormal methodologyVMM/OVM/UVMCollaboration skillsTeamwork skills

Required

Minimum 3 years experience with SystemVerilog and UVM
Minimum 2 years experience with coding functional coverage (based off of SystemVerilog)
Minimum 2 years experience with scripting in either Python, Ruby, or C++
Minimum 1 years experience of exposure to formal methodology
Proficient in using Verilog and VMM/OVM/UVM
Experience in pre and post silicon verification test flow and automated test benches
Effective communication, collaboration, and teamwork skills
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related degree required
0-2 years of relevant experience required

Company

AllSTEM Connections

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AllSTEM Connections is a provider of staffing and recruiting services.

Funding

Current Stage
Late Stage
Company data provided by crunchbase
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Orion

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