Hardware Engineer Intern, Physical Design @ Pinnova | Jobright.ai
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Hardware Engineer Intern, Physical Design jobs in California, United States
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Pinnova ยท 1 day ago

Hardware Engineer Intern, Physical Design

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Information Technology & Services
Hiring Manager
Bisma Javed
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Responsibilities

Currently pursuing a Bachelor's, Master's, or PhD degree within Electrical Engineering, or a related field
Course or internship experience related to the following areas could be required:
Synthesis, Static Timing Analysis, Clock/Power Distribution and Analysis, RC Extraction and Correlation, Place and Route, Circuit Design
VLSI, Computer Architecture, Digital/Micro Electronics, Mixed-Signal Design, Digital Design, Logic Design
CAD and Physical Design Methodologies (flow and tools development), as well as implementation
Chip Floor Plan, Power/Clock Distribution, Chip Assembly and P&R, Timing Closure, Power and Noise Analysis, and Back-End Verification
EDA Vendor (Synopsys, Cadence, Mentor, etc.) tool suites such as: ICC2, PrimeTime, dc_shell, Innovus, SeaHawk
Depending on the internship role, prior experience or knowledge requirements could include the following programming skills and technologies:
Perl, C, C++, TCL, SPICE, Linux, Verilog, SKILL, Make, ICC2, Design Compiler, PrimeTime (Synopsys, First Encounter), Innovus, Virtuso (Cadence)

Qualification

Find out how your skills align with this job's requirements. If anything seems off, you can easily click on the tags to select or unselect skills to reflect your actual expertise.

Electrical EngineeringCircuit DesignVLSIDigital DesignEDA ToolsPerlCC++TCLSPICELinuxVerilogSKILLMakeICC2Design CompilerPrimeTimeInnovus

Required

Currently pursuing a Bachelor's, Master's, or PhD degree within Electrical Engineering, or a related field
Course or internship experience related to Synthesis, Static Timing Analysis, Clock/Power Distribution and Analysis, RC Extraction and Correlation, Place and Route, Circuit Design
Course or internship experience related to VLSI, Computer Architecture, Digital/Micro Electronics, Mixed-Signal Design, Digital Design, Logic Design
Course or internship experience related to CAD and Physical Design Methodologies (flow and tools development), as well as implementation
Course or internship experience related to Chip Floor Plan, Power/Clock Distribution, Chip Assembly and P&R, Timing Closure, Power and Noise Analysis, and Back-End Verification
Experience with EDA Vendor (Synopsys, Cadence, Mentor, etc.) tool suites such as: ICC2, PrimeTime, dc_shell, Innovus, SeaHawk
Prior experience or knowledge requirements could include programming skills and technologies such as Perl, C, C++, TCL, SPICE, Linux, Verilog, SKILL, Make, ICC2, Design Compiler, PrimeTime (Synopsys, First Encounter), Innovus, Virtuso (Cadence)

Company

Pinnova

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Pinnova is committed to helping individuals and organizations connect, grow, and achieve their potential.

Funding

Current Stage
Early Stage
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Orion

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