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Marvell Technology · 9 hours ago

Senior Principal Switch Architect

Santa Clara, CA

Full-time

Onsite

Senior Level, Lead/Staff

$177K/yr - $266K/yr

6+ years exp

Marvell Technology is a leading provider of semiconductor solutions that form the backbone of data infrastructure across various industries. The Senior Principal Switch Architect will play a pivotal role in defining the architecture of next-generation data center switches, collaborating with engineering teams to ensure high-performance and reliable products for hyperscale data centers.

DSPInternet of ThingsManufacturingSemiconductorWireless

Growth Opportunities

No H1B

U.S. Citizen Only

Hiring Manager

Jeff Shiverdaker

Responsibilities

Drive the architectural definition and modeling of next-generation Teralynx switch products

Work with multi-disciplinary engineering teams (design, verification, software, system architecture, and product) to define and validate product-level requirements

Architect high-performance, scalable, and reliable switch ASICs for hyperscale and cloud data center networks

Develop architectural and performance models to evaluate proposed features and design trade-offs

Define detailed device-level architecture, including interface specifications, buffer management, forwarding pipelines, and QoS mechanisms

Evaluate emerging technologies in networking and assess their impact on architecture choices

Collaborate with hardware and software teams throughout the product lifecycle, from concept through production

Provide comprehensive documentation and support for internal and customer-facing teams

Contribute to standardization efforts and represent Marvell in relevant industry forums as needed

Influence key technology decisions, balancing performance, scalability, power, and cost trade-offs

Interact with customers, standards bodies, and internal stakeholders to ensure architectural alignment with industry and market needs

Qualification

Switch ASIC architecturePacket processingC/C++Architecture modeling toolsPythonBuffer managementHigh-speed interconnectsCommunicationCollaboration skills

Required

Bachelor's degree in Computer Science, Electrical Engineering, or a related field with 12+ years of relevant experience – OR – Master's degree with 8+ years, – OR – Ph.D. with 6+ years

Proven experience in switch ASIC architecture, with strong understanding of packet processing, buffer management, scheduling, and high-speed interconnects

Proficiency in C/C++, Python, and architecture/performance modeling tools

Demonstrated ability to make complex architectural trade-offs involving performance, power, area, and cost

Excellent communication skills, including the ability to convey complex technical ideas to diverse audiences

Experience collaborating across geographies and functional domains