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Tensordyne · 8 months ago

Sr. ASIC EDA Workflow Engineer

San Jose, CA

Full-time

Onsite

Senior Level, Lead/Staff

10+ years exp

Recogni is a system solution company that specializes in the design of high-performance, low-power AI inferencing. In this hands-on, technology leadership role, you will lead EDA tools and DevOps systems for AI inference acceleration products, while guiding your ASIC team to enhance their workflows and EDA needs.

Artificial Intelligence (AI)SemiconductorSoftware

Responsibilities

Lead EDA tools, DevOps systems, and associated engineering workflow development for Recogni’s multimodal generative AI inference acceleration products

Guide and assist colleagues to improve and invent EDA workflows and DevOps systems within a fast-paced, agile HPC development environment

Drive Recogni’s optimization, implementation and exploration of new EDA tools and technologies for the full ASIC chip design process

Continuously innovate and improve scalable, reliable, high-performance systems and tools to enable the next generation of Recogni products

Work closely with ASIC team members engaged in the design and verification of Recogni products to understand and improve their workflows and EDA needs

Qualification

Linux system administrationEDA toolsASIC engineeringCloud-based DevOpsCMakeGNU makeNinjaCI/CDGit Branching workflowsVLSI/SoC designSynopsys toolsCadence toolsSystemVerilogC/C++PerlTCLPythonFlexLM license management

Required

10+ years expert level knowledge of Linux system administration and familiarity with cloud-based devops (IaC, CaC, etc.), with experience in supporting EDA tools in a primarily cloud-based environment (as opposed to primarily on-premises)

Experience leading the development and support for compilation, build automation, testing, packaging and installation project generators that build object files like either CMake, GNU make, and/or Ninja, as well as experience with CI/CD and modern Git Branching workflows

Hands-on ASIC engineering experience, that includes knowledge of VLSI/SoC chip design and verification workflows, with ASIC EDA tool suites from Synopsys and/or Cadence, for physically-aware logic synthesis, RTL and gate-level simulation, structural analysis (CDC, RDC, etc.) and lint tools, ECO creation and LEC tools, and other commonly-used parts of the ASIC development ecosystem

Programming and debugging skills with SystemVerilog as well as with key languages to automate tasks and improve efficiency like C/C++, Perl, TCL and Python, with experience developing tools for design verification scripting as well as HDL code generators and scripts for creating hard macros from higher level descriptions

Prior work experience with onboarding and supporting ASIC engineers with EDA workflows, including installation of new tool versions, FlexLM license management, and debugging/fixing issues with EDA vendors

Excellent analytical, written, and verbal interpersonal skills along with an ability to productively collaborate within a global engineering team that moves at a startup pace

Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering or a related technical field