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Marvell Technology · 1 week ago

Senior Principal Engineer - Design For Test (DFT)

Morrisville, NC

Full-time

Onsite

Senior Level, Lead/Staff

$171K/yr - $253K/yr

15+ years exp

Marvell Technology is a leader in semiconductor solutions that connect the world across various domains. They are seeking a Digital IC Design Senior Principal Engineer to architect, lead, and implement DFT/Test on complex IP and SOC designs, while also mentoring a team of engineers.

DSPInternet of ThingsManufacturingSemiconductorWireless

Growth Opportunities

No H1B

U.S. Citizen Only

Responsibilities

The position will be responsible for architecting, leading and implementing DFT/Test on complex IP and SOC for multiple custom/compute ASIC/SoC designs

The execution involves Design-for-Test architecture definition, implementation of various DFT/DFX features, validation, IP-DFT, STA, pattern generation & post-silicon bring-up and debug for various designs/IPs in Custom/Compute space

In this position, the responsibility also includes mentoring, guiding and driving a small team of engineers enabling them for scaling across multiple designs

The position also involves definition and enhancement of DFT methodologies and tools to be able to benchmark them and enable new methodologies in the domain of DFT/Test

Qualification

DFT architecture definitionCustom chip designDFT execution functionsDigital circuit designSiemens/Synopsys Tool setScripting skillsTeam leadershipProblem solvingCommunication

Required

Bachelor's, Master's degree or PhD in Computer Science, Electrical Engineering or related fields with minimum of 15 years of work experience

Direct DFT experience with at least 12 years in the custom chip design business

Led the DFT execution on several ASICs. Was responsible for all DFT execution functions from architecture definition to tape out through silicon bring-up

Hands-on working experience in various stages of DFT-Execution: SCAN/MBIST/Validation/STA/IP-DFX/Post-Silicon Bring-up/Debug

Thorough knowledge on various DFT/Test architecture solutions and should be involved in DFT-Architecture definition of at-least five monolithic designs. These designs should have been at or approaching reticle limits

Thorough knowledge on various DFT/Test architecture solutions for 2.5D/3D IC design and should be involved in DFT-Architecture definition of at-least couple of MCM designs

Strong fundamentals in digital circuit design and logic design

Understanding of DFT flows and methodologies and experience with Siemens/Synopsys Tool set (Tessent, Spyglass/Tmax, Genus, Modus, NCSim/DC)

Proven track record of problem solving and innovation to meet challenging design requirements

Excellent team player and can work with different function leaders, across different geographies to define and execute the DFT project to completion

Excellent communications skill both verbal and written