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Marvell Technology · 1 week ago

Design Verification Engineer, Senior Staff

Santa Clara, CA

Full-time

Onsite

Senior Level, Lead/Staff

$124K/yr - $186K/yr

5+ years exp

Marvell Technology is a leading provider of semiconductor solutions that drive innovations across various sectors including cloud and AI. The role involves developing the architecture for a functional verification environment, collaborating with engineers, and ensuring the verification of complex ASIC and SOC designs.

DSPInternet of ThingsManufacturingSemiconductorWireless

Growth Opportunities

No H1B

U.S. Citizen Only

Responsibilities

Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers

Work closely with architects/RTL engineers to bring-up a new architecture/micro-architecture on the verification environment

Develop testbench components in Systemverilog, UVM, C, and C++. Write tests in Systemverilog, UVM, C, C++, python to test various logical features in ASIC and SOC design blocks

Debug failures in tests and root cause issues with test environment and design

Write a verification test plan using random techniques and coverage analysis, and work with designers to ensure it is complete

Develop tests and tune the environment to achieve coverage goals

Own and debug failures in simulation to root cause problems

Architecting, developing, and maintaining tools to streamline the design of state-of-the-art multicore SoCs

Analysis/closure of code and functional coverage

Qualification

Functional verification techniquesSystem VerilogC++Digital design principlesEthernet networkingDynamic environment adaptabilityProblem-solving skillsCommunication skillsCollaboration skills