Astera Labs · 3 days ago
Technical Lead Design Verification Engineer
San Jose, CA
Full-time
Onsite
Senior Level, Lead/Staff
$147K/yr - $195K/yr
5+ years expAstera Labs is a company providing rack-scale AI infrastructure through innovative connectivity solutions. They are seeking a Technical Lead Design Verification Engineer to lead the verification of complex ASICs, utilizing coding and problem-solving skills throughout the verification lifecycle.
AutomotiveElectronicsIntelligent SystemsSemiconductor
Responsibilities
Contribute to the functional verification of the designs
Responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage
Work with the software and system validation teams to come up with test plans and executing them in emulation platforms
Develop test-plans, and related test-sequences to generate stimuli and work collaboratively with RTL designers to debug failures
Identify and write all types of coverage measures for stimulus and corner-cases
Close coverage to identify verification holes for high quality tape-out
Qualification
Required
Strong academic and technical background in electrical engineering
At minimum, a Bachelor's in EE is required, and a Masters is preferred
≥5 years' experience verifying and validating complex SoC for Server, Storage, and Networking applications
Knowledge of industry-standard simulators, revision control systems, and regression systems
Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision
Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
Authorized to work in the US and start immediately
Experience with full verification lifecycle based on System Verilog/UVM/C/C++
Proven ability to mix and deploy hybrid techniques as in both directed and constrained random
Experience with different ways to bug and coverage hunting
Must be able to work independently to develop test-plans, and related test-sequences to generate stimuli and work collaboratively with RTL designers to debug failures
Identify and write all types of coverage measures for stimulus and corner-cases
Close coverage to identify verification holes for high quality tape-out
Preferred
Working experience with scripting tools (Perl/Python) to automate verification infrastructure
Prior experience using Verification IPs from 3rd party vendors with one or more communication protocols such as PCI-Express (Gen-3 and above), Ethernet, InfiniBand, DDR4/5, NVMe, USB, etc
Experience with directed test based methodologies, cache verification and formal methods
Company
Astera Labs
Astera Labs is a semiconductor company that provides connectivity solutions for intelligent systems.
201-500 employees
H1B Sponsorship
Astera Labs has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (50)
2024 (44)
2023 (17)
2022 (26)
2021 (14)
2020 (7)
Funding
Current Stage
Public CompanyTotal Funding
$206.35MKey Investors
Fidelity
2024-03-20IPO
2022-11-17Series D· $150M
2021-09-27Series C· $50M
Leadership Team
Jitendra Mohan
CEO
Casey Morrison
Chief Product Officer, Co-Founder
Recent News
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2026-01-07
2025-12-29
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