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MatX · 5 months ago

ASIC/SOC Micro-Architect and RTL Design Engineer

Mountain View, CA

Full-time

Onsite

Mid, Senior Level

0+ years exp

MatX is on a mission to be the compute platform for AGI, developing full-stack solutions from silicon to systems for large ML workloads. They are seeking silicon micro-architects and design engineers to deliver high-performance and functionally accurate silicon for their products across various technologies.

AI InfrastructureArtificial Intelligence (AI)HardwareManufacturingSemiconductor

No H1B

Responsibilities

Contribute to MatX’s silicon architecture-to-design methodology with a scalable solution across blocks, subsystems, fullchip design

Own entire subsystem or subsets and/or chip-level silicon design deliverables from micro-architecture to sign-off ready design

Plan and drive intermediate and sign-off reviews on micro-architecture and design specifications, execution progress, area and timing closure towards various silicon milestones including design freeze and tapeout

Work closely with the verification, DFT and physical design co-owners of the subsystem/block in question and deliver best-in-class performance-power-area results

Qualification

ASIC design experienceSOC design experienceSystemVerilogC/C++PythonBluespecSilicon micro-architectureDesign synthesisDFT conceptsSilicon debugEmulation platformsSoft skills

Required

Concept-to-silicon experience in driving silicon design for subsystems and/or top-level functions with ASICs and SOCs from an architecture specification to production silicon

Experience with SystemVerilog, Python, C/C++, Bluespec and similar scripting and programming languages for chip design and related flows

Production-proven experience on silicon micro-architecture and design concepts used in high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity, memory management and related functionalities

Experience with testing your designs and working closely with verification teams towards performance and coverage closure goals

Hands-on experience with design synthesis, equivalence checking, design lint, clock-domain-crossing and related flows to take designs to high quality sign-off

Experience on DFT and physical design concepts and methodologies to achieve high test coverage and best-in-class timing, power and area for designs working with experts in these areas to take designs to sign-off

Familiarity with verification, emulation platforms and methodologies is a plus

Hands-on experience with participation in silicon debug and bring-up is a plus