Astera Labs · 4 months ago
Principal Physical Design Engineer (STA)
San Jose, CA
Full-time
Onsite
Lead/Staff
$209K/yr - $250K/yr
12+ years expAstera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. As a Principal Physical Design Engineer (STA), you will be responsible for driving the planning, coordination, and execution supporting the design of connectivity ASICs for leading cloud service providers and network OEMs, working closely with various engineering teams.
AutomotiveElectronicsIntelligent SystemsSemiconductor
Responsibilities
Play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs
Work closely with designers, verification engineering, and engineering operations
Develop and maintain timing constraints, timing signoff methodology, and timing closure at the block and full-chip level
Own full chip or block level from architecture to GDSII, driving multiple complex designs to production
Utilize Cadence and/or Synopsys physical design tools/flows
Apply good scripting skills in tcl, python, or Perl
Qualification
Required
Strong academic and technical background in electrical engineering
A bachelor's degree in EE / Computer Science is required
≥12 years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications
Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision
Entrepreneurial, open-minded behavior and a can-do attitude
Proven expertise in developing/maintaining timing constraints, timing signoff methodology, and timing closure at the block and full-chip level
Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less
Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production
Experience with Cadence and/or Synopsys physical design tools/flows
Familiarity and working knowledge of System Verilog/Verilog
Experience with DFT tools and techniques
Experience in working with IP vendors for both RTL and hard-macro blocks
Good scripting skills in tcl, python, or Perl
Preferred
Good knowledge of design for test (DFT), stuck-at and transition scan test insertion
Familiarity with DFT test coverage and debug
Familiarity with ECO methodologies and tools
Company
Astera Labs
Astera Labs is a semiconductor company that provides connectivity solutions for intelligent systems.
201-500 employees
H1B Sponsorship
Astera Labs has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (50)
2024 (44)
2023 (17)
2022 (26)
2021 (14)
2020 (7)
Funding
Current Stage
Public CompanyTotal Funding
$206.35MKey Investors
Fidelity
2024-03-20IPO
2022-11-17Series D· $150M
2021-09-27Series C· $50M
Leadership Team
Jitendra Mohan
CEO
Casey Morrison
Chief Product Officer, Co-Founder
Recent News
The Motley Fool
2026-01-07
2025-12-29
Company data provided by crunchbase