Astera Labs · 3 weeks ago
Principal Physical Design Engineer (STA)
San Jose, CA
Full-time
Onsite
Lead/Staff
$209K/yr - $250K/yr
10+ years expAstera Labs is a provider of rack-scale AI infrastructure through purpose-built connectivity solutions. They are seeking a Principal Physical Design Engineer (STA) to drive the planning, coordination, and execution of the design of connectivity ASICs, ensuring robust full-chip timing convergence through close collaboration with various teams.
AutomotiveElectronicsIntelligent SystemsSemiconductor
Responsibilities
Drive timing closure from RTL through sign-off, ensuring robust timing across complex SoCs
Develop and validate SDC constraints, including MMMC setup, to enable accurate and efficient STA analysis
Define and manage I/O timing budgets across hierarchical designs
Apply advanced sign-off methodologies at TSMC 7nm and below, including OCV/AOCV and PVT effects
Leverage ETM libraries for hierarchical timing analysis and correlation, balancing runtime and accuracy
Provide actionable timing feedback at both block and full-chip levels, including root cause analysis and ECO guidance
Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage
Generate and validate timing ECOs, partnering with physical design and RTL teams for quick closure
Partner closely with design, implementation, and verification teams to drive timing convergence, providing sign-off level expertise and guidance
Qualification
Required
Bachelor's in Electrical Engineering or Computer Science required; Master's preferred
≥10 years of experience in timing analysis and sign-off for complex SoCs in Server, Storage, or Networking applications
Expertise in timing constraints, STA methodology, and timing closure at both block and full-chip level
Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below)
Proficiency with Cadence and/or Synopsys physical design/STA toolchains
Strong scripting ability (Tcl, Python, Perl)
Ability to work independently with strong prioritization and a professional, customer-focused mindset
Preferred
Familiarity with high-speed SERDES and Ethernet PHY timing challenges
Knowledge of ECO methodologies, DFT tools, and test coverage analysis
Experience working with IP vendors for both RTL and hard-macro integration
SystemVerilog/Verilog familiarity
Company
Astera Labs
Astera Labs is a semiconductor company that provides connectivity solutions for intelligent systems.
201-500 employees
H1B Sponsorship
Astera Labs has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
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Trends of Total Sponsorships
2025 (50)
2024 (44)
2023 (17)
2022 (26)
2021 (14)
2020 (7)
Funding
Current Stage
Public CompanyTotal Funding
$206.35MKey Investors
Fidelity
2024-03-20IPO
2022-11-17Series D· $150M
2021-09-27Series C· $50M
Leadership Team
Jitendra Mohan
CEO
Casey Morrison
Chief Product Officer, Co-Founder
Recent News
The Motley Fool
2026-01-07
2025-12-29
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