Qualcomm · 1 week ago
CPU Server Physical Design Timing Engineer
Santa Clara, CA
Full-time
Onsite
Entry, Mid Level
$142K/yr - $213K/yr
2+ years expQualcomm Technologies, Inc. is a leader in the semiconductor industry, focusing on innovative computing platforms. The CPU Server Physical Design Timing Engineer will define and drive CPU timing closure for Oryon CPU Cores, collaborating with various teams to meet performance goals and develop timing constraints.
Artificial Intelligence (AI)Generative AISoftwareTelecommunicationsWireless
Responsibilities
STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs of Oryon CPU Cores
Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus
Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation
Find out the root cause of timing miscorrelation at different design levels in functional and test mode, propose solutions
Evaluate multiple timing methodologies/tools on different designs and technology nodes
Work on automation scripts within STA/PD tools for methodology development
Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment
Strong experience in design automation using TCL/Perl/Python
Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus
Qualification
Required
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience
OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience
OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field
Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment
Strong experience in design automation using TCL/Perl/Python
Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus
Preferred
Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling
Hands-on experience with STA tools - Prime-time, Tempus
Have experience in driving timing convergence at Chip-level and Hard-Macro level
In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling
Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)
Expert in scripting languages – TCL, Perl, Python
Basic knowledge of device physics
Benefits
Competitive annual discretionary bonus program
Opportunity for annual RSU grants
Highly competitive benefits package designed to support your success at work, at home, and at play
Company
Qualcomm
Qualcomm designs wireless technologies and semiconductors that power connectivity, communication, and smart devices.
10001+ employees
H1B Sponsorship
Qualcomm has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (2013)
2024 (1910)
2023 (3216)
2022 (2885)
2021 (2104)
2020 (1181)
Funding
Current Stage
Public CompanyTotal Funding
$3.5M1991-12-20IPO
1988-01-01Undisclosed· $3.5M
Leadership Team
Cristiano Amon
President and Chief Executive Officer
I
Isaac Eteminan
CEO
Recent News
Android Authority
2026-01-09
2026-01-09
PYMNTS.com
2026-01-08
Company data provided by crunchbase