Qualcomm · 2 weeks ago
CPU Physical Design – Low Power Signoff Engineer
Santa Clara, CA
Full-time
Onsite
Mid, Senior Level
$148K/yr - $222K/yr
2+ years expQualcomm Technologies, Inc. is a leading technology innovator that drives digital transformation to create a smarter, connected future. As a CPU Physical Design – Low Power Signoff Engineer, you will take ownership of the Conformal Low Power and Formal Verification signoff for CPU subsystems, collaborating with cross-functional teams to ensure performance and low power requirements are met.
Artificial Intelligence (AI)Generative AISoftwareTelecommunicationsWireless
Responsibilities
Complete ownership on Conformal Low Power and Formal Verification signoff for hier and flat CPU Subsytem on latest nodes
Candidate should be able to handle CLP and FV signoff from synthesis to PNR exit
Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc)
Quick learner with good analytical and problem-solving skills
Qualification
Required
2-10 yrs experience in Physical Design and timing signoff for high speed cores
Should have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology
Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 2+ years of experience in IC design
Experience in leading block level or chip level Physical Design, STA and PDN activities
Work independently in the areas of RTL to GDSII implementation
Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc
Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.)
Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.)
Tcl/Perl scripting Willing to handle technical deliveries with a small team of engineers
Strong problem-solving skills
2+ years Hardware Engineering experience or related work experience
2+ years experience with PNR flow and CLP/FV runs in latest tech nodes (e.g., 4nm/5nm/7nm/10nm)
Good hands-on experience on signoff domains– LEC/CLP flows etc
Good hands-on experience on Synthesis, Floorplanning, PNR and STA flows
Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc
Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting
Complete ownership on Conformal Low Power and Formal Verification signoff for hier and flat CPU Subsytem on latest nodes
Candidate should be able to handle CLP and FV signoff from synthesis to PNR exit
Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc)
Quick learner with good analytical and problem-solving skills
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience
OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience
OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience
Benefits
Competitive annual discretionary bonus program
Annual RSU grants
Highly competitive benefits package
Company
Qualcomm
Qualcomm designs wireless technologies and semiconductors that power connectivity, communication, and smart devices.
10001+ employees
H1B Sponsorship
Qualcomm has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (2013)
2024 (1910)
2023 (3216)
2022 (2885)
2021 (2104)
2020 (1181)
Funding
Current Stage
Public CompanyTotal Funding
$3.5M1991-12-20IPO
1988-01-01Undisclosed· $3.5M
Leadership Team
Cristiano Amon
President and Chief Executive Officer
I
Isaac Eteminan
CEO
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