Lead Digital Verification Engineer jobs in United States
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Cadence ยท 2 weeks ago

Lead Digital Verification Engineer

positionMount Royal, NJ
timeFull-time
remoteOnsite
seniorityLead/Staff

Cadence is a technology company focused on developing high-performance physical IP for industry-standard protocols. The Lead Digital Verification Engineer will be responsible for the verification of digital RTL and development of reusable verification components, contributing to all aspects of digital verification including flow development and test plan execution.

AerospaceElectronic Design Automation (EDA)HardwareMobileSemiconductorSoftware
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Growth Opportunities
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H1B Sponsor Likelynote

Responsibilities

Verification of digital RTL
Development of re-usable verification components and environments
Contribute to all aspects of digital verification including flow development, test plan development and execution, functional coverage closure, and code coverage closure
Communicate with technical staff regarding overall project development progress and status
Work as part of a small and focused team of engineers
Collaborate with design teams, verification teams, project management, and digital and analog design teams in multiple worldwide geographies

Qualification

Verification architectureUniversal Verification MethodologiesSystemVerilog UVMDigital design flowMetric Driven VerificationSystem Verilog AssertionsScripting languagesStandard Protocol knowledgeProblem solvingCommunication skills

Required

Bachelor of Science in Electrical(EE)/Computer Engineering (CPE) or Computer Science (CSC)
Understanding of verification architecture and methodologies
Understanding of Metric Driven Verification
Understanding of Universal Verification Methodologies
Understanding of the identification, planning and creation of functional coverage and checks
Understanding of System Verilog Assertions (SVAs)
Understanding of digital design flow
Capable of communicating in English

Preferred

Master of Science in EE/CPE/CSC
Experience with SystemVerilog UVM coding language is desired
Experience with scripting languages such as Python, Perl, Ruby, Sed, or Awk is also strongly preferred
Exposure to Standard Protocol knowledge for any of the following areas: PCIe, USB, SATA, Ethernet, Display Port, HDMI
Exposure to Formal Verification Technologies
Exposure to Mixed Signal Design experience
Experience with Cadence tools experience
Exposure to Low Power verification experience using CPF or UPF

Company

Cadence

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Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems.
dateFounded in 1988
location
San Jose, California, USA
people-size10001+ employees
web-link
https://www.cadence.com

H1B Sponsorship

Cadence has a track record of offering H1B sponsorships. Please note that this does not guarantee sponsorship for this specific role. Below presents additional info for your reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (306)
2024 (221)
2023 (282)
2022 (330)
2021 (233)
2020 (209)

Funding

Current Stage
Public Company
Total Funding
unknown
1998-02-20IPO

Leadership Team

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Paul Cunningham
Senior Vice President and General Manager
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Tom Beckley
Senior Vice President, Custom IC & PCB Group
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Recent News

Morningstar.com
Cadence Announces Fourth Quarter and Fiscal Year 2025 Financial Results Webcast
2026-01-07
MarketScreener
Cadence Design Systems to integrate CUDA X technology into chip design software - Nvidia CEO at CES
2026-01-06
Business Wire
Cadence Launches Partner Ecosystem to Accelerate Chiplet Time to Market
2026-01-06
Company data provided by crunchbase