Broadcom · 22 hours ago
High Speed SerDes DSP RTL Designer
San Jose, CA
Full-time
Onsite
Senior Level
$120K/yr - $192K/yr
6+ years expBroadcom is looking for a high-speed DSP SerDes RTL designer. The role involves designing and implementing high-speed ADC based SerDes RTL, requiring proficiency in Verilog-HDL/System Verilog and a deep understanding of high-speed serial interconnect architectures.
MobileSemiconductorWireless
Responsibilities
Proficient with Verilog-HDL/System Verilog coding for PAM4 DSP based SerDes including equalization, adaptation and high-speed ADC calibration
Proficient with front end tools such as NCVerilog, NCSIM, Simvision, Lint
Exposure to Design for test, understanding of scan concept and writing DFT friendly RTL
Deep understanding of high-speed serial interconnect architectures such as 100G/200G per lane PAM4 and design trade-offs to drive attainment on metrics such as performance, power, and cost over the project lifetime
Experience in synthesis, CDC, static timing analysis
Exposure to SDF annotated simulations with good understanding of parasitic delays
Experience in design management with detailed knowledge of development methodologies, design flows including EDA integration, foundry PDK and associated collaterals
Strong analytical thinking and problem-solving skills with excellent attention to details
Must be organized, self-motivated and able to work effectively across internal and end customers teams
Must have excellent knowledge/experience with TSMC 7nm-2nm, i.e. understanding of power consumptions, area, estimated design and layout efforts for digital and analog blocks, technology limitations
Qualification
Required
MS or PhD in Electrical Engineering or Computer Engineering with 6+ years of experience in high speed ADC based SerDes RTL design
Proficient with Verilog-HDL/System Verilog coding for PAM4 DSP based SerDes including equalization, adaptation and high-speed ADC calibration
Proficient with front end tools such as NCVerilog, NCSIM, Simvision, Lint
Exposure to Design for test, understanding of scan concept and writing DFT friendly RTL
Deep understanding of high-speed serial interconnect architectures such as 100G/200G per lane PAM4 and design trade-offs to drive attainment on metrics such as performance, power, and cost over the project lifetime
Experience in synthesis, CDC, static timing analysis
Exposure to SDF annotated simulations with good understanding of parasitic delays
Experience in design management with detailed knowledge of development methodologies, design flows including EDA integration, foundry PDK and associated collaterals
Strong analytical thinking and problem-solving skills with excellent attention to details
Must be organized, self-motivated and able to work effectively across internal and end customers teams
Must have excellent knowledge/experience with TSMC 7nm-2nm, i.e. understanding of power consumptions, area, estimated design and layout efforts for digital and analog blocks, technology limitations
Preferred
Understanding of micro architecture with standard peripherals such as AMBA BUS/I2C/SPI/UART
Deep understanding of Signal Integrity and Power Integrity modeling for High Speed designs
Understanding & exposure to verilog AMS simulation, experience in behavioral models of analog circuit will be helpful
Benefits
Medical
Dental and vision plans
401(K) participation including company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
Company paid holidays
Paid sick leave
Vacation time
Paid Family Leave and other leaves of absence
Company
Broadcom
Broadcom is a designer, developer, and global supplier of a broad range of analog and digital semiconductor connectivity solutions.
10001+ employees
H1B Sponsorship
Broadcom has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (92)
2024 (77)
2023 (79)
2022 (112)
2021 (110)
2020 (89)
Funding
Current Stage
Public CompanyTotal Funding
unknown2017-10-31Post Ipo Equity
2015-05-28Acquired
1998-04-17IPO
Leadership Team
Greg Singh
CTO for APJ, Enterprise Security Group
Kirsten Spears
CFO and CAO, Broadcom
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