Astera Labs · 4 months ago
Senior Principal Physical Design Engineer
San Jose, CA
Full-time
Onsite
Senior Level, Lead/Staff
10+ years expAstera Labs is a company providing rack-scale AI infrastructure through connectivity solutions. They are seeking a Senior Principal Physical Design Engineer to lead the physical implementation of AI connectivity silicon, focusing on optimizing complex SoCs and mentoring engineers.
AutomotiveElectronicsIntelligent SystemsSemiconductor
Responsibilities
Lead and drive IP/macro block-level physical implementation from RTL to GDSII, focusing on timing, power, and area (PPA) optimization for high-speed SerDes and interconnect subsystems
Architect implementation strategies for AI SoCs and chiplets, supporting complex clock/power domains and hierarchical floorplans
Collaborate with RTL, STA, DFT, packaging, and verification teams to ensure timing and physical convergence
Own advanced physical design tasks including: EM/IR and power grid optimization for high-current blocks
Congestion mitigation and routing-aware floorplanning
RC-aware timing closure across corners and PVTs
Clock tree synthesis and skew management across domains
Lead chiplet integration efforts with emphasis on die-to-die interfaces, timing alignment, and physical abstraction
Drive signoff closure: DRC, LVS, antenna, ERC, and tapeout readiness using industry-standard tools (e.g., Innovus, ICC2, Calibre, Voltus, RedHawk)
Contribute to and improve physical design automation infrastructure using Tcl, Python, Perl, and other scripting tools
Act as a technical mentor, reviewing designs, guiding junior engineers, and contributing to global technical leadership
Interface with EDA vendors and TSMC for tool qualification and design enablement
Qualification
Required
Master's or PhD in Electrical or Electronics Engineering from a leading institute
10+ years of experience in physical design with multiple successful tapeouts at ≤5nm technology nodes
Strong hands-on expertise in floorplanning, placement, CTS, routing, timing, power analysis, and signoff
Proficiency with EDA tools such as Cadence Innovus, Synopsys FC, Calibre, Voltus, RedHawk
Demonstrated experience in implementing SerDes, PHYs, or high-bandwidth interconnects (e.g., PCIe, CXL)
Proven ability to collaborate across domains and lead technical efforts from spec to silicon
Preferred
Experience with AI/ML SoC designs, chiplet architectures, or UCIe interfaces
Exposure to high-speed analog/mixed-signal integration and co-design
Familiarity with signal/power integrity considerations for high-performance computing
Contributions to patents, publications, or conference presentations in the field
Company
Astera Labs
Astera Labs is a semiconductor company that provides connectivity solutions for intelligent systems.
201-500 employees
H1B Sponsorship
Astera Labs has a track record of offering H1B sponsorships. Please note that this does not
guarantee sponsorship for this specific role. Below presents additional info for your
reference. (Data Powered by US Department of Labor)
Distribution of Different Job Fields Receiving Sponsorship
Represents job field similar to this job
Trends of Total Sponsorships
2025 (50)
2024 (44)
2023 (17)
2022 (26)
2021 (14)
2020 (7)
Funding
Current Stage
Public CompanyTotal Funding
$206.35MKey Investors
Fidelity
2024-03-20IPO
2022-11-17Series D· $150M
2021-09-27Series C· $50M
Leadership Team
Jitendra Mohan
CEO
Casey Morrison
Chief Product Officer, Co-Founder
Recent News
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2026-01-07
2025-12-29
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